Simulation Results

Simulation Results: rv_dm/use_dmi_interface

09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.45 %

code
73.02 %

assert
96.66 %

func
92.68 %

block
89.69 %

line
89.52 %

branch
72.02 %

toggle
69.83 %

FSM
60.71 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	36.000s	3329.816us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	33.000s	232.383us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	210.874us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	37.000s	9094.058us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	33.000s	439.665us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	40.000s	6989.617us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	40.000s	6384.994us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	33.000s	113.234us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	67.000s	84871.200us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	274.010us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	33.000s	375.474us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	221.887us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	31.000s	109.115us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	33.000s	273.145us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	32.000s	368.759us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	30.000s	88.591us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	32.000s	551.152us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	274.010us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	30.000s	159.859us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	31.000s	196.530us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	221.887us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	30.000s	131.073us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	29.000s	143.963us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	33.000s	88.842us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	76.000s	9201.888us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	63.000s	10902.216us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	30.000s	158.461us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	63.000s	10902.216us	1	1	100.00
	rv_dm_csr_rw	33.000s	88.842us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	31.000s	46.835us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	32.000s	95.301us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	36.000s	3329.816us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	150.542us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	31.000s	342.539us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	31.000s	123.870us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	35.000s	1488.732us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	32.000s	2323.699us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	30.000s	80.614us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	30.000s	59.552us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	37.000s	18138.416us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	30.000s	511.272us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	33.000s	987.613us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	32.000s	506.518us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	34.000s	44.057us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	49.000s	13187.151us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	66.000s	8168.399us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	298.910us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	29.000s	255.784us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	50.295us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	758.953us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	758.953us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	63.000s	10902.216us	1	1	100.00
	rv_dm_csr_hw_reset	29.000s	143.963us	1	1	100.00
	rv_dm_csr_rw	33.000s	88.842us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	1103.578us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	63.000s	10902.216us	1	1	100.00
	rv_dm_csr_hw_reset	29.000s	143.963us	1	1	100.00
	rv_dm_csr_rw	33.000s	88.842us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	1103.578us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	30.000s	727.432us	1	1	100.00
	rv_dm_tl_intg_err	40.000s	1659.779us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	40.000s	1659.779us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	33.000s	987.613us	1	1	100.00
	rv_dm_debug_disabled	30.000s	97.627us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	33.000s	987.613us	1	1	100.00
	rv_dm_debug_disabled	30.000s	97.627us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	36.000s	3329.816us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	31.000s	257.946us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	320.090us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	320.090us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	31.000s	257.946us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	38.000s	1136.560us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	32.000s	0.595us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	60101071528827470097969389818169774013202175673860115453671879235203782299158	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_autoincr_sba_tl_access	30808924822086697598523955876748699040612295939444971785094430542802108480890	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24275
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	21652357634668234396162529236314353015571568966469532265643945703014431857265	107	UVM_INFO @ 80613961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	53378869239809776650969398210551760028770701989750512097453911765021479281179	107	UVM_INFO @ 59552052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	104127421079924990877459652388621333363252335681206534941897075831517636807862	87	UVM_INFO @ 511271914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	53339704031857559967470159980155618654057818919158489099666463655796506699821	88	UVM_INFO @ 255783562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	115456447386539052163164592679425006699935276932978357480499199526811497542287	87	UVM_INFO @ 109114999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	78151027700045123577941446132881007037197599820527777195020840564248077449736	87	UVM_INFO @ 44057303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_/rtl/tlul_assert.sv,381): Assertion aKnown_AKnownEnable has failed				1 test run
	rv_dm_scanmode	106670598751866876733509114902866542446266500865575857482531538244088623244804	87	UVM_ERROR @ 594615 ps: (tlul_assert.sv:381) [ASSERT FAILED] aKnown_AKnownEnable UVM_INFO @ 594615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				1 test run
	rv_dm_stress_all_with_rand_reset	4842963954092338130099030760411520317576846085559504362442387193505147517458	98	UVM_INFO @ 1136560296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---