Simulation Results: rv_timer

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.04 %
  • code
  • 90.45 %
  • assert
  • 98.10 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 69.163us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 103.233us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 43.419us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 458.909us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 20.917us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 45.241us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 43.419us 1 1 100.00
rv_timer_csr_aliasing 1.000s 20.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.000s 99.678us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 2136.622us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 276.000s 934894.995us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 276.000s 934894.995us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.000s 2483.112us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 2.000s 45.426us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 45.766us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 245.984us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 245.984us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 103.233us 1 1 100.00
rv_timer_csr_rw 1.000s 43.419us 1 1 100.00
rv_timer_csr_aliasing 1.000s 20.917us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 45.724us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 103.233us 1 1 100.00
rv_timer_csr_rw 1.000s 43.419us 1 1 100.00
rv_timer_csr_aliasing 1.000s 20.917us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 45.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 2.000s 119.478us 1 1 100.00
rv_timer_tl_intg_err 2.000s 97.747us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 97.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 3.000s 1562.201us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 46.186us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 8.000s 3399.879us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 24863800885634751396491930610426712767028296659412706239113372102721952329374 84
UVM_INFO @ 1562201002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 86870794008809365916835477486439232345715030556031699824510003824183108954030 84
UVM_INFO @ 99678066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 18324572670532162739934264286118731738685734187168387193396652287391440617284 84
UVM_INFO @ 46186290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 81100165284707500034454036655231490072007199308020669119005781267207843067 208
UVM_INFO @ 3399879044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---