Simulation Results: spi_device/1r1w

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.05 %
  • code
  • 88.82 %
  • assert
  • 95.40 %
  • func
  • 67.93 %
  • block
  • 98.37 %
  • line
  • 98.78 %
  • branch
  • 97.05 %
  • toggle
  • 69.87 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 97.000s 6152.940us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 23.849us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 41.559us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 37.000s 58232.538us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.000s 212.286us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 79.203us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 41.559us 1 1 100.00
spi_device_csr_aliasing 9.000s 212.286us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 13.677us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 188.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 35.068us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 9.989us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 14.262us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 24.775us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 24.775us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.000s 498.883us 1 1 100.00
spi_device_tpm_sts_read 1.000s 95.700us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 2.000s 22.489us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 12.000s 1669.739us 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 33.000s 5477.001us 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 33.000s 5477.001us 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.000s 256.715us 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.000s 256.715us 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.000s 256.715us 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.000s 256.715us 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.000s 256.715us 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 7.000s 1592.640us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 9.000s 3840.874us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 9.000s 3840.874us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 9.000s 3840.874us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 70.000s 27850.299us 1 1 100.00
spi_device_read_buffer_direct 14.000s 874.060us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 9.000s 3840.874us 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 101.000s 179690.948us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 222.038us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 222.038us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 364.000s 49553.303us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 97.000s 6152.940us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 326.000s 30882.557us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 179.000s 14693.492us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 46.532us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 43.736us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.000s 56.960us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.000s 56.960us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 23.849us 1 1 100.00
spi_device_csr_rw 3.000s 41.559us 1 1 100.00
spi_device_csr_aliasing 9.000s 212.286us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 75.553us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 23.849us 1 1 100.00
spi_device_csr_rw 3.000s 41.559us 1 1 100.00
spi_device_csr_aliasing 9.000s 212.286us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 75.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 261.598us 1 1 100.00
spi_device_tl_intg_err 20.000s 4132.255us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 20.000s 4132.255us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 31155315467557481026536856852038894048832509024008495607179524352413084480033 87
UVM_ERROR @ 7288753 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[927] not found within the scope .
UVM_ERROR @ 7288753 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[927] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 48224929397479374145997783127088111697494011406478949334648135998119267968709 85
UVM_ERROR @ 11943966 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x463641 [10001100011011001000001] vs 0x0 [0])
UVM_ERROR @ 12001966 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x987985 [100110000111100110000101] vs 0x0 [0])
UVM_ERROR @ 12045966 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfe16a8 [111111100001011010101000] vs 0x0 [0])
UVM_ERROR @ 12070966 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4daf2f [10011011010111100101111] vs 0x0 [0])