Simulation Results: sram_ctrl/main

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.52 %
  • code
  • 94.95 %
  • assert
  • 97.41 %
  • func
  • 91.20 %
  • block
  • 95.09 %
  • line
  • 95.72 %
  • branch
  • 92.23 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 2762.147us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 21.756us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.805us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 126.925us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 36.728us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 358.107us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 12.805us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 36.728us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 103.000s 3118.782us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 49.000s 6178.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 27.000s 4881.221us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 151.000s 5597.999us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 169.000s 72870.129us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 65.000s 65163.487us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 48.000s 49126.481us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 6460.423us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1496.103us 1 1 100.00
sram_ctrl_partial_access_b2b 152.000s 88776.931us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 1374.199us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 2640.052us 0 1 0.00
sram_ctrl_throughput_w_readback 6.000s 2653.366us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 913.960us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 852.435us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 419.000s 42545.075us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 16.591us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 110.260us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 110.260us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.756us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.805us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 36.728us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.214us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.756us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.805us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 36.728us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 7677.717us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 1491.620us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 241.295us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 1491.620us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 241.295us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 913.960us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 913.960us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.805us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 6460.423us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 6460.423us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 6460.423us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 48.000s 49126.481us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 2746.728us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 7677.717us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 3489.828us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 2762.147us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 2762.147us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 6460.423us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 1491.620us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 48.000s 49126.481us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 1491.620us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1491.620us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 2762.147us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1491.620us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 28.000s 3814.414us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 67468888140902861151164947260420762201527218775125168933614581036188106584787 86
UVM_INFO @ 1374198669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 92287881524187818586156956838963931444444929819753115163377615111989736595135 86
UVM_INFO @ 2640052055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 49973266062607939941765030869694610305683479923535605365209597409737375382626 86
UVM_INFO @ 2653365531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---