Simulation Results: sram_ctrl/ret

 
09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.64 %
  • code
  • 82.07 %
  • assert
  • 97.26 %
  • func
  • 92.60 %
  • block
  • 93.42 %
  • line
  • 94.61 %
  • branch
  • 88.73 %
  • toggle
  • 78.27 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 40.035us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 28.402us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.822us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 183.161us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 41.021us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 288.513us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 17.822us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 41.021us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 1421.605us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 346.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 507.943us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 152.000s 17902.949us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 151.713us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 17.000s 2540.049us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 2406.791us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 3.000s 188.458us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 38.080us 1 1 100.00
sram_ctrl_partial_access_b2b 119.000s 3604.652us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 85.110us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 42.626us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 147.962us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 4306.997us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 43.332us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 23.000s 5782.055us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 45.619us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 102.544us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 102.544us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 28.402us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.822us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 41.021us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 91.303us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 28.402us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.822us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 41.021us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 91.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 220.866us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 492.582us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 586.524us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 492.582us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 586.524us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 4306.997us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 4306.997us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.822us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 3.000s 188.458us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 188.458us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 188.458us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 2406.791us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 143.606us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 220.866us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 34.669us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 40.035us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 40.035us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 3.000s 188.458us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 492.582us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 2406.791us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 492.582us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 492.582us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 40.035us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 492.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 82.000s 4559.115us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 94448956943059085888061354129548330082969184581641336214140239943197054419171 86
UVM_INFO @ 85109514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 104390516824030853516290301017211786588438867315103950270788604098101527720152 86
UVM_INFO @ 42625561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 33904974073785678369098291353410374876559184791522298203894205418977949548222 86
UVM_INFO @ 147961657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---