Simulation Results

Simulation Results: uart

09/07/2026 19:39:29 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.35 %

code
92.73 %

assert
97.12 %

func
90.20 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
73.08 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	2.000s	769.433us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	34.633us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	17.540us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	3.000s	1235.384us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	2.000s	43.575us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	2.000s	20.872us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	17.540us	1	1	100.00
	uart_csr_aliasing	2.000s	43.575us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	5.000s	2945.877us	1	1	100.00
parity				2	2	100.00
	uart_smoke	2.000s	769.433us	1	1	100.00
	uart_tx_rx	5.000s	2945.877us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	29.000s	27253.003us	1	1	100.00
	uart_rx_parity_err	13.000s	39008.185us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	5.000s	2945.877us	1	1	100.00
	uart_intr	29.000s	27253.003us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	63.000s	104290.774us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	14.000s	14085.821us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	28.000s	44866.787us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	29.000s	27253.003us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	29.000s	27253.003us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	29.000s	27253.003us	1	1	100.00
perf				1	1	100.00
	uart_perf	314.000s	17922.831us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	13.000s	5618.747us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	13.000s	5618.747us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	16.000s	25256.142us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	6.000s	3146.752us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	3.000s	839.030us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	3.000s	1937.256us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	210.000s	97074.324us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	74.000s	74348.822us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	1.000s	65.111us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	13.305us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	2.000s	28.541us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	2.000s	28.541us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	1.000s	34.633us	1	1	100.00
	uart_csr_rw	1.000s	17.540us	1	1	100.00
	uart_csr_aliasing	2.000s	43.575us	1	1	100.00
	uart_same_csr_outstanding	1.000s	42.030us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	1.000s	34.633us	1	1	100.00
	uart_csr_rw	1.000s	17.540us	1	1	100.00
	uart_csr_aliasing	2.000s	43.575us	1	1	100.00
	uart_same_csr_outstanding	1.000s	42.030us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	2.000s	263.660us	1	1	100.00
	uart_tl_intg_err	2.000s	49.262us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	2.000s	49.262us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	35.000s	2903.435us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *				1 test run
	uart_noise_filter	66994991628989164656636483962364349428088017465519059421184796326851668215037	91	UVM_ERROR @ 25143021696 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 25143361696 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 25143361696 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 25235161696 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0