Simulation Results: aes/gcm_unmasked

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.48 %
  • code
  • 90.82 %
  • assert
  • 97.75 %
  • func
  • 61.88 %
  • block
  • 90.23 %
  • line
  • 92.28 %
  • branch
  • 82.31 %
  • toggle
  • 97.90 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 69.281us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 62.722us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 61.433us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 77.739us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 447.835us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 142.179us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 126.630us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 77.739us 1 1 100.00
aes_csr_aliasing 2.000s 142.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 62.722us 1 1 100.00
aes_config_error 2.000s 120.134us 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 62.722us 1 1 100.00
aes_config_error 2.000s 120.134us 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 76.219us 1 1 100.00
aes_b2b 3.000s 194.223us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 62.722us 1 1 100.00
aes_config_error 2.000s 120.134us 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
aes_alert_reset 2.000s 120.253us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 115.950us 1 1 100.00
aes_config_error 2.000s 120.134us 1 1 100.00
aes_alert_reset 2.000s 120.253us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 115.321us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 211.433us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 120.253us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 76.219us 1 1 100.00
aes_sideload 2.000s 85.574us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 90.129us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.201s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 86.999us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 384.193us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 384.193us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.433us 1 1 100.00
aes_csr_rw 2.000s 77.739us 1 1 100.00
aes_csr_aliasing 2.000s 142.179us 1 1 100.00
aes_same_csr_outstanding 2.000s 188.556us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.433us 1 1 100.00
aes_csr_rw 2.000s 77.739us 1 1 100.00
aes_csr_aliasing 2.000s 142.179us 1 1 100.00
aes_same_csr_outstanding 2.000s 188.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 231.802us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 2.000s 100.659us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 50.416us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 96.914us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 96.914us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 96.914us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 96.914us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 3133.554us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 689.223us 1 1 100.00
aes_tl_intg_err 1.000s 219.882us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 219.882us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 120.253us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 96.914us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 96.914us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 62.722us 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
aes_alert_reset 2.000s 120.253us 1 1 100.00
aes_core_fi 2.000s 64.734us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 120.134us 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
aes_core_fi 2.000s 64.734us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 96.914us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 174.433us 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 76.219us 1 1 100.00
aes_sideload 2.000s 85.574us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 174.433us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 174.433us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 174.433us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 174.433us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 174.433us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 76.219us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 100.659us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 2.000s 100.659us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 50.416us 1 1 100.00
aes_ctr_fi 2.000s 79.955us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 100.659us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 2.000s 100.659us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 50.416us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 50.416us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 100.659us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 2.000s 100.659us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 79.955us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 100.659us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 2.000s 100.659us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 50.416us 1 1 100.00
aes_ctr_fi 2.000s 79.955us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 120.253us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 2.000s 100.659us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 50.416us 1 1 100.00
aes_ctr_fi 2.000s 79.955us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 2.000s 100.659us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 50.416us 1 1 100.00
aes_ctr_fi 2.000s 79.955us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 2.000s 100.659us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 79.955us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 100.659us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 2.000s 100.659us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 50.416us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 51.512us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
aes_control_fi 105141845238094496733293885937190496251256716895484239830104946215895211086518 None
aes_stress_all 94086653216632137025146985695860314286132813391789927410483787912281048334929 None
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 1972389002853704592848610156038201972169383081060597216238331353432515519279 5305
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 61418736810075787102731941082482382125331109649127643305993975587329861408395 251
UVM_INFO @ 51512170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---