Simulation Results: alert_handler

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.53 %
  • code
  • 90.27 %
  • assert
  • 98.29 %
  • func
  • 80.02 %
  • line
  • 99.69 %
  • branch
  • 98.36 %
  • cond
  • 90.58 %
  • toggle
  • 88.54 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 7.370s 247.353us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.890s 269.222us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.340s 151.916us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 507.710s 50215.266us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 54.650s 2532.876us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.370s 209.539us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.340s 151.916us 1 1 100.00
alert_handler_csr_aliasing 54.650s 2532.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 138.280s 7409.684us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 37.460s 1067.911us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2191.530s 105920.738us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 24.770s 832.857us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 7.370s 247.353us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 43.870s 1155.509us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 66.340s 1624.262us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 27.560s 874.814us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2354.430s 64345.769us 1 1 100.00
alert_handler_lpg_stub_clk 1719.570s 224636.343us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1319.100s 85031.263us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 10.920s 1246.418us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.750s 71.231us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.760s 7.171us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.270s 105.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.270s 105.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.890s 269.222us 1 1 100.00
alert_handler_csr_rw 4.340s 151.916us 1 1 100.00
alert_handler_csr_aliasing 54.650s 2532.876us 1 1 100.00
alert_handler_same_csr_outstanding 16.010s 449.375us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.890s 269.222us 1 1 100.00
alert_handler_csr_rw 4.340s 151.916us 1 1 100.00
alert_handler_csr_aliasing 54.650s 2532.876us 1 1 100.00
alert_handler_same_csr_outstanding 16.010s 449.375us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 133.910s 6671.844us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 133.910s 6671.844us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 133.910s 6671.844us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 133.910s 6671.844us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 474.340s 5574.467us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
alert_handler_tl_intg_err 9.940s 308.019us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 9.940s 308.019us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 133.910s 6671.844us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 7.370s 247.353us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 7.370s 247.353us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 7.370s 247.353us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 7.370s 247.353us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.770s 832.857us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2354.430s 64345.769us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.770s 832.857us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2191.530s 105920.738us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2191.530s 105920.738us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 8.790s 962.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 45.360s 1755.130us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 3943680554800332268893750495765166010553643725841304033704936043873296524300 84
UVM_INFO @ 874813843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 90152443405405603623971112241847341071848619783578617450514620641675584703049 212
UVM_INFO @ 1246417581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 11636884295383315766909414129751903374884499114268720382193566027912168078980 84
UVM_INFO @ 1755129989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---