Simulation Results: clkmgr

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.09 %
  • code
  • 69.24 %
  • assert
  • 86.36 %
  • func
  • 66.67 %
  • line
  • 82.07 %
  • branch
  • 87.53 %
  • cond
  • 76.96 %
  • toggle
  • 99.62 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.440s 94.587us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.080s 52.935us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.780s 12.820us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.160s 32.086us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.850s 48.246us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.130s 25.977us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.780s 12.820us 0 1 0.00
clkmgr_csr_aliasing 1.850s 48.246us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.800s 25.217us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.820s 150.497us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.400s 86.552us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.440s 94.587us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.740s 10.872us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.640s 3.368us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.740s 10.872us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.680s 5.140us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.980s 19.412us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.910s 71.193us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.910s 71.193us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.080s 52.935us 1 1 100.00
clkmgr_csr_rw 0.780s 12.820us 0 1 0.00
clkmgr_csr_aliasing 1.850s 48.246us 1 1 100.00
clkmgr_same_csr_outstanding 0.610s 2.487us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.080s 52.935us 1 1 100.00
clkmgr_csr_rw 0.780s 12.820us 0 1 0.00
clkmgr_csr_aliasing 1.850s 48.246us 1 1 100.00
clkmgr_same_csr_outstanding 0.610s 2.487us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.510s 206.058us 1 1 100.00
clkmgr_tl_intg_err 1.050s 28.437us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.050s 40.605us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.050s 40.605us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.050s 40.605us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.050s 40.605us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.670s 5.822us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.050s 28.437us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.740s 10.872us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.640s 3.368us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.050s 40.605us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.990s 49.721us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.780s 12.820us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.510s 206.058us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.780s 12.820us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.780s 12.820us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.510s 206.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.620s 3.096us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.520s 40.408us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 103749764204595768356258892926990477709479886565610952744609504847434275357058 76
UVM_INFO @ 10872320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 100623512948385754121795008952840612645857238536042166787512815314941436596089 78
UVM_INFO @ 40407635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 68031640336288417887730671603485919594877571415847734140698236546173226797913 78
UVM_INFO @ 3367767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 11149160053483501900231702627924821100254437264152916995654489259490503048860 78
UVM_INFO @ 5140392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_tl_intg_err 25570361531717332453979315102648625897422432636050754784420113822287119875656 105
UVM_INFO @ 28437194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 70814712238494913392471017757049303653709021675012463995548881968819746546652 75
UVM_INFO @ 12819568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 1104466094230488520914568317778945360677843277234822242972291869941233681208 74
UVM_INFO @ 3096199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 6140332202348480533551209378554468683989323915314848660335817949450758562044 75
UVM_INFO @ 5821665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 92560626492386133149695698426489434383040276254310808635810068041642793345628 75
UVM_INFO @ 32085509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 57409425201928116203668659748369641104981790944488096339039677665014386460616 75
UVM_INFO @ 2486562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---