Simulation Results: dma

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.28 %
  • code
  • 90.38 %
  • assert
  • 96.50 %
  • func
  • 65.96 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1407.281us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 498.899us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 291.030us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 28.942us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 13.619us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 929.434us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 563.355us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 33.604us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 13.619us 1 1 100.00
dma_csr_aliasing 6.000s 563.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 54.000s 19175.536us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 823.000s 119385.630us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 152.000s 78857.504us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 152.000s 78857.504us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 823.000s 119385.630us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 923.000s 387449.327us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 152.000s 78857.504us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 8.000s 530.890us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 209.000s 102270.607us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 49.658us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 46.779us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 89.891us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 89.891us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 28.942us 1 1 100.00
dma_csr_rw 2.000s 13.619us 1 1 100.00
dma_csr_aliasing 6.000s 563.355us 1 1 100.00
dma_same_csr_outstanding 2.000s 66.402us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 28.942us 1 1 100.00
dma_csr_rw 2.000s 13.619us 1 1 100.00
dma_csr_aliasing 6.000s 563.355us 1 1 100.00
dma_same_csr_outstanding 2.000s 66.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 19.000s 1827.786us 1 1 100.00
dma_generic_stress 923.000s 387449.327us 1 1 100.00
dma_handshake_stress 152.000s 78857.504us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 1516.293us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 223.706us 1 1 100.00
dma_sec_cm 1.000s 20.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 120.000s 42755.538us 1 1 100.00
dma_longer_transfer 2.000s 74.112us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 104.189us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 16189479161767944167477814240402344116837247471186461867081007329519428665379 98
UVM_INFO @ 104188868ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---