Simulation Results: edn/edn0

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.57 %
  • code
  • 82.40 %
  • assert
  • 94.25 %
  • func
  • 50.07 %
  • block
  • 93.86 %
  • line
  • 96.83 %
  • branch
  • 86.85 %
  • toggle
  • 66.08 %
  • FSM
  • 79.84 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 27.435us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 42.288us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 14.527us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.000s 48.757us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 31.466us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 45.841us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 14.527us 1 1 100.00
edn_csr_aliasing 1.000s 31.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 46.100us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 46.100us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 46.100us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 19.977us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 28.158us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 33.018us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 41.977us 1 1 100.00
edn_disable_auto_req_mode 1.000s 55.812us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.000s 171.709us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 49.610us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 27.562us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 65.629us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 65.629us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 42.288us 1 1 100.00
edn_csr_rw 2.000s 14.527us 1 1 100.00
edn_csr_aliasing 1.000s 31.466us 1 1 100.00
edn_same_csr_outstanding 2.000s 35.236us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 42.288us 1 1 100.00
edn_csr_rw 2.000s 14.527us 1 1 100.00
edn_csr_aliasing 1.000s 31.466us 1 1 100.00
edn_same_csr_outstanding 2.000s 35.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 411.046us 1 1 100.00
edn_tl_intg_err 2.000s 55.595us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 19.223us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 28.158us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 411.046us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 411.046us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 411.046us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 411.046us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 28.158us 1 1 100.00
edn_sec_cm 4.000s 411.046us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 28.158us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 55.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 58.000s 13499.592us 1 1 100.00