Simulation Results: edn/edn1

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.29 %
  • code
  • 82.48 %
  • assert
  • 98.44 %
  • func
  • 77.94 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 89.08 %
  • toggle
  • 87.29 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 18.030us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.010s 16.261us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 13.633us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.740s 124.499us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.010s 26.683us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.140s 24.422us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 13.633us 1 1 100.00
edn_csr_aliasing 1.010s 26.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.350s 267.043us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.350s 267.043us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.350s 267.043us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.970s 26.798us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.220s 99.705us 1 1 100.00
errs 1 1 100.00
edn_err 0.900s 22.689us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 11.605us 1 1 100.00
edn_disable_auto_req_mode 0.790s 17.534us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.090s 454.928us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 15.603us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 31.408us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.010s 231.790us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.010s 231.790us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.010s 16.261us 1 1 100.00
edn_csr_rw 0.750s 13.633us 1 1 100.00
edn_csr_aliasing 1.010s 26.683us 1 1 100.00
edn_same_csr_outstanding 0.990s 17.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.010s 16.261us 1 1 100.00
edn_csr_rw 0.750s 13.633us 1 1 100.00
edn_csr_aliasing 1.010s 26.683us 1 1 100.00
edn_same_csr_outstanding 0.990s 17.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.290s 176.615us 1 1 100.00
edn_tl_intg_err 1.880s 72.490us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 30.654us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.220s 99.705us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.290s 176.615us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.290s 176.615us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.290s 176.615us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.290s 176.615us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.220s 99.705us 1 1 100.00
edn_sec_cm 2.290s 176.615us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.220s 99.705us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.880s 72.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 29.160s 1762.854us 1 1 100.00