Simulation Results: hmac

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.41 %
  • code
  • 96.00 %
  • assert
  • 97.17 %
  • func
  • 30.06 %
  • block
  • 97.51 %
  • line
  • 98.44 %
  • branch
  • 93.76 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.000s 316.146us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 31.221us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 60.409us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.000s 3389.597us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 326.443us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 18.458us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 60.409us 1 1 100.00
hmac_csr_aliasing 3.000s 326.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 9.000s 662.352us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 34.000s 1054.412us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 11.000s 490.650us 1 1 100.00
hmac_test_sha384_vectors 355.000s 13291.162us 1 1 100.00
hmac_test_sha512_vectors 436.000s 36082.603us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 2840.711us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 400.998us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 5508.576us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 24.000s 1125.538us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 147.000s 4314.182us 1 1 100.00
error 1 1 100.00
hmac_error 39.000s 3951.982us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 59.000s 7803.297us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.000s 316.146us 1 1 100.00
hmac_long_msg 9.000s 662.352us 1 1 100.00
hmac_back_pressure 34.000s 1054.412us 1 1 100.00
hmac_datapath_stress 147.000s 4314.182us 1 1 100.00
hmac_burst_wr 24.000s 1125.538us 1 1 100.00
hmac_stress_all 240.000s 30006.821us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.000s 316.146us 1 1 100.00
hmac_long_msg 9.000s 662.352us 1 1 100.00
hmac_back_pressure 34.000s 1054.412us 1 1 100.00
hmac_datapath_stress 147.000s 4314.182us 1 1 100.00
hmac_wipe_secret 59.000s 7803.297us 1 1 100.00
hmac_test_sha256_vectors 11.000s 490.650us 1 1 100.00
hmac_test_sha384_vectors 355.000s 13291.162us 1 1 100.00
hmac_test_sha512_vectors 436.000s 36082.603us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 2840.711us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 400.998us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 5508.576us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.000s 316.146us 1 1 100.00
hmac_long_msg 9.000s 662.352us 1 1 100.00
hmac_back_pressure 34.000s 1054.412us 1 1 100.00
hmac_datapath_stress 147.000s 4314.182us 1 1 100.00
hmac_burst_wr 24.000s 1125.538us 1 1 100.00
hmac_error 39.000s 3951.982us 1 1 100.00
hmac_wipe_secret 59.000s 7803.297us 1 1 100.00
hmac_test_sha256_vectors 11.000s 490.650us 1 1 100.00
hmac_test_sha384_vectors 355.000s 13291.162us 1 1 100.00
hmac_test_sha512_vectors 436.000s 36082.603us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 2840.711us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 400.998us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 5508.576us 1 1 100.00
hmac_stress_all 240.000s 30006.821us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 240.000s 30006.821us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 13.672us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 24.192us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 557.106us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 557.106us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 31.221us 1 1 100.00
hmac_csr_rw 1.000s 60.409us 1 1 100.00
hmac_csr_aliasing 3.000s 326.443us 1 1 100.00
hmac_same_csr_outstanding 3.000s 160.757us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 31.221us 1 1 100.00
hmac_csr_rw 1.000s 60.409us 1 1 100.00
hmac_csr_aliasing 3.000s 326.443us 1 1 100.00
hmac_same_csr_outstanding 3.000s 160.757us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 66.599us 1 1 100.00
hmac_tl_intg_err 2.000s 502.989us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 502.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.000s 316.146us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 1040.151us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 45.000s 12706.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 11.775us 1 1 100.00