Simulation Results

Simulation Results: i2c

13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.37 %

code
86.44 %

assert
97.46 %

func
81.22 %

block
96.20 %

line
95.60 %

branch
93.20 %

toggle
72.80 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	231.000s	1330.069us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	8.000s	886.251us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	62.060us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	17.717us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.000s	631.317us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	28.733us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	45.679us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	17.717us	1	1	100.00
	i2c_csr_aliasing	2.000s	28.733us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	27.248us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1.000s	35.481us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	4.000s	420.998us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	32.324us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1098.000s	9484.944us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	172.258us	1	1	100.00
	i2c_host_fifo_fmt_empty	20.000s	718.743us	1	1	100.00
	i2c_host_fifo_reset_rx	3.000s	112.498us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	777.000s	2272.341us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	12.000s	592.372us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	4.000s	90.164us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.000s	5735.841us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	1075.000s	19152.138us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	4288.566us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	8.000s	2009.764us	1	1	100.00
	i2c_target_intr_smoke	4.000s	7473.549us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	269.207us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	294.778us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	220.000s	31359.507us	1	1	100.00
	i2c_target_stress_rd	8.000s	2009.764us	1	1	100.00
	i2c_target_intr_stress_wr	4.000s	424.949us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	5782.139us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	349.000s	2559.766us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	10.000s	15720.344us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	3.000s	203.042us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	2906.006us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	313.120us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	4.000s	420.998us	1	1	100.00
	i2c_host_perf_precise	1631.000s	5767.961us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	12.000s	592.372us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.000s	79.447us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	6.000s	3769.343us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	475.418us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	592.360us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.000s	2182.582us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	418.206us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	31.058us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	31.034us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	191.394us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	191.394us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	62.060us	1	1	100.00
	i2c_csr_rw	1.000s	17.717us	1	1	100.00
	i2c_csr_aliasing	2.000s	28.733us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	173.981us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	62.060us	1	1	100.00
	i2c_csr_rw	1.000s	17.717us	1	1	100.00
	i2c_csr_aliasing	2.000s	28.733us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	173.981us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	129.065us	1	1	100.00
	i2c_sec_cm	2.000s	145.446us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	129.065us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	5.000s	618.007us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	19.470us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	5.000s	379.007us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	54713802584200997833177377758946709018067010040410306616899445173122708975427	89	UVM_INFO @ 27247779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	11579779328690694396677115616832866216758652948778288100287110154055575541599	95	UVM_INFO @ 35481256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	35189038028844359297358721821940731937495666580442851619347587353935013185060	101	UVM_INFO @ 618006730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	112471145968206865088471571135588783644674009413688441468053959049894221601546	94	UVM_INFO @ 379007473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	i2c_host_fifo_watermark	109010644184196005008758402777944613305924849763644473409992902040042918593469	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	103453747124189755535774007920191543052928246645726638912172032045518249397328	93	UVM_INFO @ 5735840658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	107079901624105767347245703156181705075217049873631775956287548377203485637580	87	UVM_INFO @ 19469574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:629) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	46245701793330352577712609644962571256237702530307045267175370687775155117707	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------