| V1 |
|
83.33% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| keymgr_dpe_smoke | 10.000s | 236.179us | 0 | 1 | 0.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.000s | 18.629us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_rw | 2.000s | 79.321us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_bit_bash | 5.000s | 131.437us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_aliasing | 4.000s | 538.639us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 3.000s | 73.909us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| keymgr_dpe_csr_rw | 2.000s | 79.321us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.000s | 538.639us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_intr_test | 1.000s | 13.083us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_alert_test | 1.000s | 50.503us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 3.000s | 78.187us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 3.000s | 78.187us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.000s | 18.629us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 2.000s | 79.321us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.000s | 538.639us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 2.000s | 50.339us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.000s | 18.629us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 2.000s | 79.321us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.000s | 538.639us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 2.000s | 50.339us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| keymgr_dpe_sec_cm | 10.000s | 1166.054us | 1 | 1 | 100.00 | |
| keymgr_dpe_tl_intg_err | 6.000s | 1009.109us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 3.000s | 63.156us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 3.000s | 63.156us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 3.000s | 63.156us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 3.000s | 63.156us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 5.000s | 850.632us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 10.000s | 1166.054us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 10.000s | 1166.054us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert recov_operation_err has unexpected timeout error | 1 test run | |||
| keymgr_dpe_smoke | 9991536446852355487896352737964424263106119037943045274794223550623364895504 | 3483 |
UVM_INFO @ 236179206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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