Simulation Results

Simulation Results: kmac/masked

13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
79.96 %

code
67.19 %

assert
96.48 %

func
76.21 %

line
95.19 %

branch
89.20 %

cond
83.63 %

toggle
29.31 %

FSM
38.61 %

Validation stages

V1		100.00%
V2		68.97%
V2S		75.00%
V3		0.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	kmac_smoke	48.370s	3820.720us	1	1	100.00
csr_hw_reset				1	1	100.00
	kmac_csr_hw_reset	1.170s	38.022us	1	1	100.00
csr_rw				1	1	100.00
	kmac_csr_rw	1.110s	144.458us	1	1	100.00
csr_bit_bash				1	1	100.00
	kmac_csr_bit_bash	16.670s	1870.642us	1	1	100.00
csr_aliasing				1	1	100.00
	kmac_csr_aliasing	5.530s	272.253us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	kmac_csr_mem_rw_with_rand_reset	1.590s	87.030us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	kmac_csr_rw	1.110s	144.458us	1	1	100.00
	kmac_csr_aliasing	5.530s	272.253us	1	1	100.00
mem_walk				1	1	100.00
	kmac_mem_walk	0.780s	39.712us	1	1	100.00
mem_partial_access				1	1	100.00
	kmac_mem_partial_access	1.350s	50.158us	1	1	100.00

20/29 passed

68.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				1	1	100.00
	kmac_long_msg_and_output	667.490s	245201.937us	1	1	100.00
burst_write				1	1	100.00
	kmac_burst_write	397.760s	14096.421us	1	1	100.00
test_vectors				8	8	100.00
	kmac_test_vectors_sha3_224	29.500s	12326.349us	1	1	100.00
	kmac_test_vectors_sha3_256	30.980s	9552.713us	1	1	100.00
	kmac_test_vectors_sha3_384	1585.430s	86089.013us	1	1	100.00
	kmac_test_vectors_sha3_512	19.790s	17025.709us	1	1	100.00
	kmac_test_vectors_shake_128	129.100s	14031.065us	1	1	100.00
	kmac_test_vectors_shake_256	2342.160s	334127.176us	1	1	100.00
	kmac_test_vectors_kmac	2.190s	100.901us	1	1	100.00
	kmac_test_vectors_kmac_xof	2.510s	277.399us	1	1	100.00
sideload				1	1	100.00
	kmac_sideload	240.910s	49536.226us	1	1	100.00
app				0	1	0.00
	kmac_app	9.340s	768.379us	0	1	0.00
app_with_partial_data				0	1	0.00
	kmac_app_with_partial_data	2.950s	178.987us	0	1	0.00
entropy_refresh				0	1	0.00
	kmac_entropy_refresh	3.410s	654.332us	0	1	0.00
error				0	1	0.00
	kmac_error	100.360s	22419.330us	0	1	0.00
key_error				0	1	0.00
	kmac_key_error	1.220s	104.498us	0	1	0.00
sideload_invalid				0	1	0.00
	kmac_sideload_invalid	1.020s	5.086us	0	1	0.00
edn_timeout_error				1	1	100.00
	kmac_edn_timeout_error	7.980s	2059.082us	1	1	100.00
entropy_mode_error				1	1	100.00
	kmac_entropy_mode_error	11.590s	696.335us	1	1	100.00
entropy_ready_error				0	1	0.00
	kmac_entropy_ready_error	1.510s	69.898us	0	1	0.00
lc_escalation				0	1	0.00
	kmac_lc_escalation	0.940s	24.006us	0	1	0.00
stress_all				0	1	0.00
	kmac_stress_all	1.200s	1281.111us	0	1	0.00
intr_test				1	1	100.00
	kmac_intr_test	0.870s	13.719us	1	1	100.00
alert_test				1	1	100.00
	kmac_alert_test	1.230s	53.841us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	kmac_tl_errors	2.650s	323.832us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	kmac_tl_errors	2.650s	323.832us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	kmac_csr_hw_reset	1.170s	38.022us	1	1	100.00
	kmac_csr_rw	1.110s	144.458us	1	1	100.00
	kmac_csr_aliasing	5.530s	272.253us	1	1	100.00
	kmac_same_csr_outstanding	2.080s	922.081us	1	1	100.00
tl_d_partial_access				4	4	100.00
	kmac_csr_hw_reset	1.170s	38.022us	1	1	100.00
	kmac_csr_rw	1.110s	144.458us	1	1	100.00
	kmac_csr_aliasing	5.530s	272.253us	1	1	100.00
	kmac_same_csr_outstanding	2.080s	922.081us	1	1	100.00

V2S

6/8 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				1	1	100.00
	kmac_shadow_reg_errors	1.680s	280.635us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	kmac_shadow_reg_errors	1.680s	280.635us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	kmac_shadow_reg_errors	1.680s	280.635us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	kmac_shadow_reg_errors	1.680s	280.635us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	kmac_shadow_reg_errors_with_csr_rw	2.330s	475.580us	1	1	100.00
tl_intg_err				2	2	100.00
	kmac_sec_cm	35.230s	5495.921us	1	1	100.00
	kmac_tl_intg_err	5.530s	688.736us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	kmac_tl_intg_err	5.530s	688.736us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				0	1	0.00
	kmac_lc_escalation	0.940s	24.006us	0	1	0.00
sec_cm_sw_key_key_masking				1	1	100.00
	kmac_smoke	48.370s	3820.720us	1	1	100.00
sec_cm_key_sideload				1	1	100.00
	kmac_sideload	240.910s	49536.226us	1	1	100.00
sec_cm_cfg_shadowed_config_shadow				1	1	100.00
	kmac_shadow_reg_errors	1.680s	280.635us	1	1	100.00
sec_cm_fsm_sparse				1	1	100.00
	kmac_sec_cm	35.230s	5495.921us	1	1	100.00
sec_cm_ctr_redun				1	1	100.00
	kmac_sec_cm	35.230s	5495.921us	1	1	100.00
sec_cm_packer_ctr_redun				1	1	100.00
	kmac_sec_cm	35.230s	5495.921us	1	1	100.00
sec_cm_cfg_shadowed_config_regwen				1	1	100.00
	kmac_smoke	48.370s	3820.720us	1	1	100.00
sec_cm_fsm_global_esc				0	1	0.00
	kmac_lc_escalation	0.940s	24.006us	0	1	0.00
sec_cm_fsm_local_esc				1	1	100.00
	kmac_sec_cm	35.230s	5495.921us	1	1	100.00
sec_cm_absorbed_ctrl_mubi				0	1	0.00
	kmac_mubi	3.690s	1266.304us	0	1	0.00
sec_cm_sw_cmd_ctrl_sparse				1	1	100.00
	kmac_smoke	48.370s	3820.720us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	kmac_stress_all_with_rand_reset	25.150s	4888.198us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [] vs []) Mismatch between unmasked_digest[] and dpi_digest[*]				6 test runs
	kmac_app	26750827635500101339759871710579817809004224352065703319769328359472465304959	80	UVM_INFO @ 768378984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_app_with_partial_data	54975099839085621990370892368318753434236545942344732301758911654852275431351	78	UVM_INFO @ 178987262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_refresh	6330602605745852780833628349316380750475427967188656772893120029441937294788	78	UVM_INFO @ 654331722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_error	73289388152738138713694995759083289246858022030436820249969088877888607373653	133	UVM_INFO @ 22419329594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_lc_escalation	68967946946544065405186056462823833170631222051487578873314492352523417850449	80	UVM_INFO @ 24006281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all	95249712268580842881469928248535265957396084791378370277020197557995179594499	79	UVM_INFO @ 1281111273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))'				3 test runs
	kmac_sideload_invalid	100475370842952161121270299511202907669556079927421683390427398147879241651248	79	UVM_ERROR @ 5085535 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A UVM_INFO @ 5085535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_key_error	13958272378990796525024943819728541940775920160853442454945468021445139862932	78	UVM_ERROR @ 104497530 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A UVM_INFO @ 104497530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_ready_error	5129279927039674386724080541273004265874253994980878478402213662759211111656	78	UVM_ERROR @ 69897825 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A UVM_INFO @ 69897825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err)				2 test runs
	kmac_mubi	80294514030227036607043968928027462919729951111789378183171606843427320074968	79	UVM_INFO @ 1266303776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all_with_rand_reset	60217138298627639396236693490189246883635151111451811923799566423781004231085	132	UVM_INFO @ 4888198289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---