Simulation Results: lc_ctrl/volatile_unlock_disabled

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.12 %
  • code
  • 92.61 %
  • assert
  • 96.83 %
  • func
  • 86.94 %
  • block
  • 96.61 %
  • line
  • 97.29 %
  • branch
  • 91.38 %
  • toggle
  • 86.51 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 36.048us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 59.286us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 175.611us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 25.882us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 38.732us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 20.363us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 175.611us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 38.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 776.564us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 6141.500us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.971us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 125.985us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.000s 1151.378us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_ctrl_prog_failure 2.000s 125.985us 1 1 100.00
lc_ctrl_errors 3.000s 1151.378us 1 1 100.00
lc_ctrl_security_escalation 7.000s 3116.730us 1 1 100.00
lc_ctrl_jtag_state_failure 59.000s 4101.222us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 519.525us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 1672.347us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 751.481us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 2840.665us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 519.525us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 1672.347us 1 1 100.00
lc_ctrl_jtag_access 3.000s 688.388us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 937.588us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 334.566us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 82.326us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.000s 897.912us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 12.000s 794.228us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 186.801us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 103.398us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 47.714us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 1238.929us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 15.299us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.000s 2074.416us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 40.565us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 654.150us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 654.150us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 59.286us 1 1 100.00
lc_ctrl_csr_rw 2.000s 175.611us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 38.732us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 21.675us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 59.286us 1 1 100.00
lc_ctrl_csr_rw 2.000s 175.611us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 38.732us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 21.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 1647.056us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 308.102us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 308.102us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 6141.500us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_ctrl_sec_cm 2.000s 1647.056us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_ctrl_sec_cm 2.000s 1647.056us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_ctrl_sec_cm 2.000s 1647.056us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_ctrl_sec_cm 2.000s 1647.056us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_ctrl_sec_cm 2.000s 1647.056us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_ctrl_sec_cm 2.000s 1647.056us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_ctrl_sec_cm 2.000s 1647.056us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.000s 819.612us 1 1 100.00
lc_ctrl_sec_cm 2.000s 1647.056us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 3116.730us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 776.564us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 2840.665us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 344.377us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 344.377us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.000s 426.566us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 2804.480us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 2804.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 28.000s 3057.744us 1 1 100.00