Simulation Results: lc_ctrl/volatile_unlock_enabled

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.89 %
  • code
  • 93.47 %
  • assert
  • 96.54 %
  • func
  • 85.67 %
  • block
  • 96.98 %
  • line
  • 97.57 %
  • branch
  • 92.33 %
  • toggle
  • 86.34 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 34.786us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.060us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 43.838us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 69.721us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.269us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 102.890us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 43.838us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 741.895us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 2396.853us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 51.552us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 100.925us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.000s 792.097us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_ctrl_prog_failure 3.000s 100.925us 1 1 100.00
lc_ctrl_errors 8.000s 792.097us 1 1 100.00
lc_ctrl_security_escalation 5.000s 1440.991us 1 1 100.00
lc_ctrl_jtag_state_failure 12.000s 1652.075us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 455.880us 1 1 100.00
lc_ctrl_jtag_errors 18.000s 2398.842us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 161.195us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 698.122us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.000s 455.880us 1 1 100.00
lc_ctrl_jtag_errors 18.000s 2398.842us 1 1 100.00
lc_ctrl_jtag_access 3.000s 238.034us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.000s 1355.425us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 5.000s 867.332us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 303.799us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 900.031us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 316.514us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 212.453us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 3899.858us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 315.209us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 373.919us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 12.661us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 195.000s 60293.601us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 17.678us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 668.701us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 668.701us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.060us 1 1 100.00
lc_ctrl_csr_rw 1.000s 43.838us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.269us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 36.980us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.060us 1 1 100.00
lc_ctrl_csr_rw 1.000s 43.838us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.269us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 36.980us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 285.251us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 179.024us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 179.024us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 2396.853us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_ctrl_sec_cm 3.000s 285.251us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_ctrl_sec_cm 3.000s 285.251us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_ctrl_sec_cm 3.000s 285.251us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_ctrl_sec_cm 3.000s 285.251us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_ctrl_sec_cm 3.000s 285.251us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_ctrl_sec_cm 3.000s 285.251us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_ctrl_sec_cm 3.000s 285.251us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 467.622us 1 1 100.00
lc_ctrl_sec_cm 3.000s 285.251us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 1440.991us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 741.895us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 698.122us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 883.148us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 883.148us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 15691.829us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 185.605us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 185.605us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 15.000s 2958.907us 1 1 100.00