Simulation Results: otbn

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.95 %
  • code
  • 84.69 %
  • assert
  • 87.68 %
  • func
  • 94.49 %
  • block
  • 99.22 %
  • line
  • 99.42 %
  • branch
  • 94.48 %
  • toggle
  • 81.47 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 12.000s 52.406us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 171.872us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 56.588us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 41.159us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 105.618us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 58.417us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 245.322us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 41.159us 1 1 100.00
otbn_csr_aliasing 4.000s 58.417us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 98.000s 1489.336us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 15.000s 692.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 26.000s 69.688us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 64.000s 675.330us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 24.000s 57.838us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 39.000s 162.088us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 16.000s 40.438us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 44.212us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 43.637us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 16.058us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 39.870us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 245.005us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 245.005us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 56.588us 1 1 100.00
otbn_csr_rw 4.000s 41.159us 1 1 100.00
otbn_csr_aliasing 4.000s 58.417us 1 1 100.00
otbn_same_csr_outstanding 5.000s 27.253us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 56.588us 1 1 100.00
otbn_csr_rw 4.000s 41.159us 1 1 100.00
otbn_csr_aliasing 4.000s 58.417us 1 1 100.00
otbn_same_csr_outstanding 5.000s 27.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 60.350us 1 1 100.00
otbn_dmem_err 10.000s 63.977us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 8.000s 16.591us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 222.463us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 24.600us 1 1 100.00
otbn_urnd_err 5.000s 8.552us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 9.000s 38.977us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 39.933us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 69.537us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
otbn_tl_intg_err 21.000s 145.676us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 29.000s 203.789us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 52.406us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 63.977us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 60.350us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 21.000s 145.676us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 16.000s 40.438us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 60.350us 1 1 100.00
otbn_dmem_err 10.000s 63.977us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 44.212us 1 1 100.00
otbn_illegal_mem_acc 9.000s 38.977us 1 1 100.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 171.872us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 60.350us 1 1 100.00
otbn_dmem_err 10.000s 63.977us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 44.212us 1 1 100.00
otbn_illegal_mem_acc 9.000s 38.977us 1 1 100.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 16.000s 40.438us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 60.350us 1 1 100.00
otbn_dmem_err 10.000s 63.977us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 44.212us 1 1 100.00
otbn_illegal_mem_acc 9.000s 38.977us 1 1 100.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 171.872us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 8.000s 49.175us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 112.915us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 46.000s 431.062us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 46.000s 431.062us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 11.000s 29.957us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 13.000s 64.567us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 28.663us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 28.663us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 7.000s 12.440us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 171.872us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 171.872us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 171.872us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 24.000s 57.838us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 171.872us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 171.872us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 18.000s 434.448us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 171.872us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 11.000s 167.799us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 102.000s 450.731us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 40.082us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 27437238350780849752226623709244611445430224386288640430016199757106586459841 211
UVM_INFO @ 450731179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_urnd_err 42501669070485440141195166359884423902021010679257118765099201418315205782231 119
UVM_INFO @ 8551613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 54992463412342400054102014953593179559253758851585977184002159343363701379747 104
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 167798646 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 167798646 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 167798646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---