Simulation Results: rom_ctrl/64kb

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.26 %
  • code
  • 93.45 %
  • assert
  • 97.67 %
  • func
  • 97.65 %
  • block
  • 95.34 %
  • line
  • 95.36 %
  • branch
  • 93.82 %
  • toggle
  • 84.62 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 268.768us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.000s 221.379us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.000s 308.076us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 217.855us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 367.881us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 1064.135us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.000s 308.076us 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 367.881us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.000s 1026.446us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.000s 3559.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 5.000s 1840.062us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 18.000s 1063.106us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 9.000s 1272.400us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.000s 524.710us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 294.503us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.000s 294.503us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 221.379us 1 1 100.00
rom_ctrl_csr_rw 6.000s 308.076us 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 367.881us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 211.508us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 221.379us 1 1 100.00
rom_ctrl_csr_rw 6.000s 308.076us 1 1 100.00
rom_ctrl_csr_aliasing 6.000s 367.881us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 211.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.000s 5680.021us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 197.000s 2624.567us 1 1 100.00
rom_ctrl_tl_intg_err 48.000s 548.868us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 197.000s 2624.567us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 197.000s 2624.567us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 197.000s 2624.567us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 197.000s 2624.567us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 268.768us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 268.768us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 268.768us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 48.000s 548.868us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
rom_ctrl_kmac_err_chk 9.000s 1272.400us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.000s 58827.046us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 25.000s 5680.021us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 197.000s 2624.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 71.000s 3080.211us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 100796331012120957948288078791933228676065658653110813727006525626849255003605 88
UVM_INFO @ 1840061575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---