Simulation Results: rstmgr

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.50 %
  • code
  • 99.27 %
  • assert
  • 98.35 %
  • func
  • 94.88 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.75 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.310s 71.671us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.070s 63.417us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.820s 37.788us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.440s 210.088us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.140s 44.668us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.980s 67.026us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.820s 37.788us 1 1 100.00
rstmgr_csr_aliasing 1.140s 44.668us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.430s 147.192us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.990s 46.451us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.110s 39.970us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.070s 673.442us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.070s 673.442us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.070s 673.442us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.070s 673.442us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 5.380s 903.509us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.230s 37.980us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.810s 45.358us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.810s 45.358us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.070s 63.417us 1 1 100.00
rstmgr_csr_rw 0.820s 37.788us 1 1 100.00
rstmgr_csr_aliasing 1.140s 44.668us 1 1 100.00
rstmgr_same_csr_outstanding 0.860s 37.008us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.070s 63.417us 1 1 100.00
rstmgr_csr_rw 0.820s 37.788us 1 1 100.00
rstmgr_csr_aliasing 1.140s 44.668us 1 1 100.00
rstmgr_same_csr_outstanding 0.860s 37.008us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 15.640s 3410.762us 1 1 100.00
rstmgr_tl_intg_err 5.470s 719.978us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 15.640s 3410.762us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 15.640s 3410.762us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 5.470s 719.978us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.120s 65.288us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.930s 482.795us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.060s 291.796us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 15.640s 3410.762us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 37.788us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.820s 37.788us 1 1 100.00