Simulation Results

Simulation Results: rv_dm/use_dmi_interface

13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
89.96 %

code
81.42 %

assert
96.74 %

func
91.74 %

block
92.46 %

line
93.15 %

branch
79.51 %

toggle
72.64 %

FSM
80.36 %

Validation stages

V1		96.30%
V2		73.91%
V2S		85.71%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	35.000s	1579.405us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	31.000s	589.922us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	31.000s	853.038us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	35.000s	7455.643us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	31.000s	2463.931us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	35.000s	3398.672us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	38.000s	5408.269us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	38.000s	10142.119us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	317.000s	270310.863us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	37.000s	868.520us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	33.000s	439.695us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	649.731us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	34.000s	420.904us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	31.000s	536.012us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	30.000s	215.487us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	32.000s	76.705us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	33.000s	895.230us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	37.000s	868.520us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	31.000s	143.765us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	32.000s	568.358us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	32.000s	649.731us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	31.000s	196.626us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	31.000s	305.655us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	32.000s	424.791us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	47.000s	10545.393us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	46.000s	2819.989us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	32.000s	223.732us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	46.000s	2819.989us	1	1	100.00
	rv_dm_csr_rw	32.000s	424.791us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	31.000s	65.421us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	30.000s	160.675us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	35.000s	1579.405us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	233.777us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	30.000s	151.547us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	30.000s	150.389us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	32.000s	722.262us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	36.000s	6254.214us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	31.000s	52.562us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	32.000s	731.769us	0	1	0.00
sba_autoincrement				1	1	100.00
	rv_dm_autoincr_sba_tl_access	50.000s	29547.487us	1	1	100.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	30.000s	477.322us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	33.000s	1775.130us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	30.000s	563.480us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	30.000s	80.406us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	37.000s	5509.067us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	43.000s	18414.007us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	147.846us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	10808.107s	0.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	76.333us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	589.618us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	589.618us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	2819.989us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	305.655us	1	1	100.00
	rv_dm_csr_rw	32.000s	424.791us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	490.051us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	2819.989us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	305.655us	1	1	100.00
	rv_dm_csr_rw	32.000s	424.791us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	490.051us	1	1	100.00

V2S

6/7 passed

85.71 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	32.000s	934.432us	1	1	100.00
	rv_dm_tl_intg_err	35.000s	1804.536us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	35.000s	1804.536us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	33.000s	1775.130us	1	1	100.00
	rv_dm_debug_disabled	31.000s	50.422us	0	1	0.00
sec_cm_lc_dft_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	33.000s	1775.130us	1	1	100.00
	rv_dm_debug_disabled	31.000s	50.422us	0	1	0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	35.000s	1579.405us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	31.000s	368.419us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	116.243us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	116.243us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	31.000s	368.419us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	35.000s	1224.052us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	112.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	51303860046675220690728350326184437942095486230400272869371824548745722756894	107	UVM_INFO @ 52561751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	37138732203865285251549975195976923850447691291568185387405722275554671518564	107	UVM_INFO @ 731769290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	26353233641846932116000924964059736596609020116601098105851722093277914586813	87	UVM_INFO @ 420903796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	79865554239501685569265257357056462900789069704104438579956428411445339750384	121	UVM_INFO @ 1224051671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				1 test run
	rv_dm_sba_tl_access	30986230542125298278173411690384253693121492079729547242007055091884921283387	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23873
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	6189397838992358664298365347590868511189876613217031569924115957552066779380	87	UVM_INFO @ 80406151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	113419808839183805594494776435884356784943973992148283028120436137446522357581	87	UVM_INFO @ 477321584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)				1 test run
	rv_dm_debug_disabled	7045090832860156547890695898716587253138108955785645375734695143397896539567	89	UVM_INFO @ 50422414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	70257272214491893423643991316247745307079890168361797497755904883581869259640	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	rv_dm_stress_all	66105107984597736662820777448927753874191369246377762739865901106401134807073	None