Simulation Results: rv_timer

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 90.45 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 87.301us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 15.797us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 14.851us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.000s 48.974us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 28.724us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 30.331us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 14.851us 1 1 100.00
rv_timer_csr_aliasing 2.000s 28.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 4.000s 4172.407us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 3450.201us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 76.000s 89653.463us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 76.000s 89653.463us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.000s 1308.138us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 15.917us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 42.217us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 693.429us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 693.429us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.797us 1 1 100.00
rv_timer_csr_rw 1.000s 14.851us 1 1 100.00
rv_timer_csr_aliasing 2.000s 28.724us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 88.229us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.797us 1 1 100.00
rv_timer_csr_rw 1.000s 14.851us 1 1 100.00
rv_timer_csr_aliasing 2.000s 28.724us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 88.229us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 872.531us 1 1 100.00
rv_timer_tl_intg_err 2.000s 1424.299us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 1424.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 75.627us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 604.565us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 26.000s 2839.993us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 8530044665839542480799990436156519959960721032121050857364748877273940858883 84
UVM_INFO @ 75627014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 31959649377239209301971476162080938737334390637971352446547995111813585171362 85
UVM_INFO @ 4172407402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 90325890895124393950767807236998845421181004955964310227827196108866692827572 84
UVM_INFO @ 604564820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---