Simulation Results: spi_device/1r1w

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.22 %
  • code
  • 88.79 %
  • assert
  • 95.40 %
  • func
  • 68.48 %
  • block
  • 98.33 %
  • line
  • 98.76 %
  • branch
  • 96.96 %
  • toggle
  • 69.87 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 39.000s 8805.937us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 17.502us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 4.000s 410.444us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 33.000s 4312.407us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 12.000s 300.334us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 187.163us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 4.000s 410.444us 1 1 100.00
spi_device_csr_aliasing 12.000s 300.334us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 14.226us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 58.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 35.272us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 1.261us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 7.348us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 82.689us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 82.689us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.000s 1612.850us 1 1 100.00
spi_device_tpm_sts_read 1.000s 12.610us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 6.000s 945.139us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 17.000s 3850.434us 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 26.000s 19272.120us 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 26.000s 19272.120us 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.000s 356.380us 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.000s 356.380us 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.000s 356.380us 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.000s 356.380us 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.000s 356.380us 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 25.000s 4167.477us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 48.000s 4631.619us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 48.000s 4631.619us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 48.000s 4631.619us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 32.000s 2241.605us 1 1 100.00
spi_device_read_buffer_direct 9.000s 786.909us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 48.000s 4631.619us 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 265.000s 35069.990us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 118.774us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 118.774us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 383.000s 190086.753us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 39.000s 8805.937us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 19.000s 6872.176us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 71.000s 2903.377us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 26.866us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 15.143us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 6.000s 221.555us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 6.000s 221.555us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 17.502us 1 1 100.00
spi_device_csr_rw 4.000s 410.444us 1 1 100.00
spi_device_csr_aliasing 12.000s 300.334us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 489.768us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 17.502us 1 1 100.00
spi_device_csr_rw 4.000s 410.444us 1 1 100.00
spi_device_csr_aliasing 12.000s 300.334us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 489.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 155.904us 1 1 100.00
spi_device_tl_intg_err 14.000s 299.289us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 14.000s 299.289us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 104900504928366556135010309688084475695911029906241038972192339466814863092600 87
UVM_ERROR @ 1042210 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[920] not found within the scope .
UVM_ERROR @ 1042210 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[920] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 55513151893904692393882806681781747224910118136406237649517097518228512014140 85
UVM_ERROR @ 4966285 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3bcf6b [1110111100111101101011] vs 0x0 [0])
UVM_ERROR @ 5040285 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd32c23 [110100110010110000100011] vs 0x0 [0])
UVM_ERROR @ 5111285 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf50ca9 [111101010000110010101001] vs 0x0 [0])
UVM_ERROR @ 5179285 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb5a225 [101101011010001000100101] vs 0x0 [0])