Simulation Results: sram_ctrl/main

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.73 %
  • code
  • 94.91 %
  • assert
  • 97.28 %
  • func
  • 95.00 %
  • block
  • 95.03 %
  • line
  • 95.72 %
  • branch
  • 92.07 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 375.341us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 12.838us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.179us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 367.166us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.822us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 365.980us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 41.179us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.822us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 116.000s 46369.796us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 57.000s 25243.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 3135.012us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 88.000s 6285.313us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 118.000s 13354.945us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 35.000s 23649.418us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 9613.111us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 5625.454us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 678.484us 1 1 100.00
sram_ctrl_partial_access_b2b 95.000s 14384.175us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 2640.647us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 1326.392us 0 1 0.00
sram_ctrl_throughput_w_readback 8.000s 13266.100us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 3483.491us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 470.237us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 194.000s 27652.043us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 13.044us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 20.396us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 20.396us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 12.838us 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.179us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.822us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 51.539us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 12.838us 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.179us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.822us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 51.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 47226.954us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 186.109us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 155.585us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 186.109us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 155.585us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 3483.491us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 3483.491us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.179us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 5625.454us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 5625.454us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 5625.454us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 9613.111us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 1351.405us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 47226.954us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 1393.634us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 375.341us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 375.341us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 5625.454us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 186.109us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 9613.111us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 186.109us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 186.109us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 375.341us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 186.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 31.000s 4079.611us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 114042191046266806278358367910045110299201731166597762651459155554891388675229 86
UVM_INFO @ 2640646790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 101666936010855836218016737417885862858986143183470625397893480147212946709686 86
UVM_INFO @ 1326391713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 32043185613354060902499588310029704518566624673639736144082692057785723043543 86
UVM_INFO @ 13266100386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---