Simulation Results: sram_ctrl/ret

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.02 %
  • code
  • 82.12 %
  • assert
  • 97.94 %
  • func
  • 93.00 %
  • block
  • 93.49 %
  • line
  • 94.61 %
  • branch
  • 88.89 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 133.270us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 11.554us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 188.140us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 1149.463us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.378us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 44.356us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 188.140us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.378us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 866.688us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 184.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 549.538us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 111.000s 2432.522us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 273.079us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 8.000s 292.608us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1811.619us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 2795.106us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 248.234us 1 1 100.00
sram_ctrl_partial_access_b2b 117.000s 39412.558us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 51.410us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 105.627us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 44.082us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 454.811us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 27.538us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 17.000s 3244.275us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 14.561us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 258.682us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 258.682us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 11.554us 1 1 100.00
sram_ctrl_csr_rw 2.000s 188.140us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.378us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 31.981us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 11.554us 1 1 100.00
sram_ctrl_csr_rw 2.000s 188.140us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.378us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 31.981us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 830.205us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 443.266us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 455.965us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 443.266us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 455.965us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 454.811us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 454.811us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 188.140us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 2795.106us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 2795.106us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 2795.106us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1811.619us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 70.600us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 830.205us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 50.154us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 133.270us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 133.270us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 2795.106us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 443.266us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1811.619us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 443.266us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 443.266us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 133.270us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 443.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 61.000s 3565.105us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 40066417605496024592464437680919967745554105954577546831647043505190961511100 86
UVM_INFO @ 51409569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 37269853626666052976828814772080872243926859235730870374679544403139560589960 86
UVM_INFO @ 105626728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 109012874427765771806869280725073708002439209308902885543502560930930281760543 86
UVM_INFO @ 44082265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---