Simulation Results: uart

 
13/07/2026 19:40:35 DVSim: v1.49.12 sha: 68eb7b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.74 %
  • code
  • 73.69 %
  • assert
  • 98.85 %
  • func
  • 90.69 %
  • block
  • 98.66 %
  • line
  • 99.24 %
  • branch
  • 97.42 %
  • toggle
  • 73.08 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 294.694us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 14.756us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 2.000s 69.214us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 534.627us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 25.714us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 108.322us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 2.000s 69.214us 1 1 100.00
uart_csr_aliasing 1.000s 25.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 28.000s 68150.907us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 294.694us 1 1 100.00
uart_tx_rx 28.000s 68150.907us 1 1 100.00
parity_error 2 2 100.00
uart_intr 43.000s 221060.967us 1 1 100.00
uart_rx_parity_err 10.000s 6576.885us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 28.000s 68150.907us 1 1 100.00
uart_intr 43.000s 221060.967us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 98.000s 83766.064us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 40.000s 34245.255us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 16.000s 20025.211us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 43.000s 221060.967us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 43.000s 221060.967us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 43.000s 221060.967us 1 1 100.00
perf 1 1 100.00
uart_perf 32.000s 5391.418us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.000s 8638.961us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.000s 8638.961us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 5.000s 10860.301us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.000s 44534.595us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.000s 1270.409us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 8.000s 6075.980us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 590.000s 148254.891us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 14.000s 10267.105us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 23.728us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 63.702us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 774.354us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 774.354us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 14.756us 1 1 100.00
uart_csr_rw 2.000s 69.214us 1 1 100.00
uart_csr_aliasing 1.000s 25.714us 1 1 100.00
uart_same_csr_outstanding 1.000s 92.901us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 14.756us 1 1 100.00
uart_csr_rw 2.000s 69.214us 1 1 100.00
uart_csr_aliasing 1.000s 25.714us 1 1 100.00
uart_same_csr_outstanding 1.000s 92.901us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 74.293us 1 1 100.00
uart_tl_intg_err 1.000s 89.632us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 89.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 24.000s 2476.840us 1 1 100.00