Simulation Results: ac_range_check

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.81 %
  • code
  • 92.97 %
  • assert
  • 97.75 %
  • func
  • 57.70 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 21.000s 2039.838us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 40.000s 9603.153us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 18.482us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 520.421us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 21.000s 732.764us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 18.000s 5652.642us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 96.628us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 520.421us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 5652.642us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 89.475us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 22.000s 2092.540us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 129.000s 3004.570us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 17.507us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 11.764us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 1567.007us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 1567.007us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 18.482us 1 1 100.00
ac_range_check_csr_rw 2.000s 520.421us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 5652.642us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 2100.330us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 18.482us 1 1 100.00
ac_range_check_csr_rw 2.000s 520.421us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 5652.642us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 2100.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 1281.816us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 1281.816us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 1281.816us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 1281.816us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 77.000s 4531.241us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 39.326us 1 1 100.00
ac_range_check_tl_intg_err 5.000s 232.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 218.000s 2938.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 25.000s 1396.204us 1 1 100.00