| V1 |
|
100.00% |
| V2 |
|
94.74% |
| V2S |
|
94.44% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 3.000s | 466.608us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| aes_smoke | 2.000s | 67.858us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 99.032us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aes_csr_rw | 2.000s | 53.042us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 4.000s | 297.397us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 2.000s | 153.927us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 2.000s | 60.590us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aes_csr_rw | 2.000s | 53.042us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 153.927us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 3 | 3 | 100.00 | |||
| aes_smoke | 2.000s | 67.858us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 111.695us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| key_length | 3 | 3 | 100.00 | |||
| aes_smoke | 2.000s | 67.858us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 111.695us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| back2back | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| aes_b2b | 11.000s | 238.643us | 1 | 1 | 100.00 | |
| backpressure | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| multi_message | 4 | 4 | 100.00 | |||
| aes_smoke | 2.000s | 67.858us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 111.695us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| aes_alert_reset | 5.000s | 118.173us | 1 | 1 | 100.00 | |
| failure_test | 3 | 3 | 100.00 | |||
| aes_man_cfg_err | 2.000s | 76.235us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 111.695us | 1 | 1 | 100.00 | |
| aes_alert_reset | 5.000s | 118.173us | 1 | 1 | 100.00 | |
| trigger_clear_test | 1 | 1 | 100.00 | |||
| aes_clear | 3.000s | 120.442us | 1 | 1 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 19.000s | 7677.661us | 1 | 1 | 100.00 | |
| nist_test_vectors_gcm | 1 | 1 | 100.00 | |||
| aes_nist_vectors_gcm | 7.000s | 1207.050us | 1 | 1 | 100.00 | |
| reset_recovery | 1 | 1 | 100.00 | |||
| aes_alert_reset | 5.000s | 118.173us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| sideload | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| aes_sideload | 4.000s | 123.705us | 1 | 1 | 100.00 | |
| deinitialization | 1 | 1 | 100.00 | |||
| aes_deinit | 3.000s | 80.939us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| aes_stress_all | 5.000s | 240.079us | 0 | 1 | 0.00 | |
| gcm_save_and_restore | 1 | 1 | 100.00 | |||
| aes_gcm_save_restore | 3.000s | 122.125us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aes_alert_test | 1.000s | 84.776us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 2.000s | 134.811us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 2.000s | 134.811us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 99.032us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 53.042us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 153.927us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 1.000s | 109.978us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 99.032us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 53.042us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 2.000s | 153.927us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 1.000s | 109.978us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 1 | 1 | 100.00 | |||
| aes_reseed | 2.000s | 319.529us | 1 | 1 | 100.00 | |
| fault_inject | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 68.364us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 3.000s | 73.811us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 279.714us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 279.714us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 279.714us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 279.714us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 3.000s | 183.951us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| aes_sec_cm | 4.000s | 3157.285us | 1 | 1 | 100.00 | |
| aes_tl_intg_err | 1.000s | 245.320us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aes_tl_intg_err | 1.000s | 245.320us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| aes_alert_reset | 5.000s | 118.173us | 1 | 1 | 100.00 | |
| sec_cm_main_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 279.714us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 279.714us | 1 | 1 | 100.00 | |
| sec_cm_main_config_sparse | 4 | 4 | 100.00 | |||
| aes_smoke | 2.000s | 67.858us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| aes_alert_reset | 5.000s | 118.173us | 1 | 1 | 100.00 | |
| aes_core_fi | 2.000s | 86.034us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_sparse | 4 | 4 | 100.00 | |||
| aes_gcm_save_restore | 3.000s | 122.125us | 1 | 1 | 100.00 | |
| aes_config_error | 2.000s | 111.695us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| aes_core_fi | 2.000s | 86.034us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 2.000s | 279.714us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_regwen | 2 | 2 | 100.00 | |||
| aes_readability | 2.000s | 85.967us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| aes_sideload | 4.000s | 123.705us | 1 | 1 | 100.00 | |
| sec_cm_key_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 85.967us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 85.967us | 1 | 1 | 100.00 | |
| sec_cm_key_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 85.967us | 1 | 1 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 85.967us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 85.967us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_key_sca | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| sec_cm_key_masking | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 66.784us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_redun | 3 | 4 | 75.00 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 68.364us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 3.000s | 73.811us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 3.000s | 100.742us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| sec_cm_cipher_fsm_redun | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 68.364us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 3.000s | 73.811us | 1 | 1 | 100.00 | |
| sec_cm_cipher_ctr_redun | 1 | 1 | 100.00 | |||
| aes_cipher_fi | 3.000s | 73.811us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| sec_cm_ctr_fsm_redun | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 68.364us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 3.000s | 100.742us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_sparse | 3 | 4 | 75.00 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 68.364us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 3.000s | 73.811us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 3.000s | 100.742us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| aes_alert_reset | 5.000s | 118.173us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 3 | 4 | 75.00 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 68.364us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 3.000s | 73.811us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 3.000s | 100.742us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 3 | 4 | 75.00 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 68.364us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 3.000s | 73.811us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 3.000s | 100.742us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 68.364us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 3.000s | 100.742us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_local_esc | 1 | 2 | 50.00 | |||
| aes_ghash_fi | 2.000s | 55.478us | 1 | 1 | 100.00 | |
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_local_esc | 2 | 3 | 66.67 | |||
| aes_fi | 3.000s | 377.132us | 0 | 1 | 0.00 | |
| aes_control_fi | 2.000s | 68.364us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 3.000s | 73.811us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| aes_stress_all_with_rand_reset | 29.000s | 1393.443us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] | 1 test run | |||
| aes_fi | 61523415606313343435543839273925354115940618284861164003227514422622556311171 | 7366 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 1 test run | |||
| aes_stress_all | 20889059771420529781284628350652632191798003760550892307832622998337197937922 | 10350 |
UVM_INFO @ 240078673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|