Simulation Results: aes/gcm_unmasked

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.43 %
  • code
  • 91.13 %
  • assert
  • 97.75 %
  • func
  • 61.42 %
  • block
  • 90.54 %
  • line
  • 92.78 %
  • branch
  • 82.96 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
88.24%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 63.832us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 60.900us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 77.945us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 415.241us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 1709.767us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 231.564us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 60.040us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 415.241us 1 1 100.00
aes_csr_aliasing 2.000s 231.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 60.900us 1 1 100.00
aes_config_error 2.000s 234.632us 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 60.900us 1 1 100.00
aes_config_error 2.000s 234.632us 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 243.185us 1 1 100.00
aes_b2b 4.000s 188.157us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 1.000s 60.900us 1 1 100.00
aes_config_error 2.000s 234.632us 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
aes_alert_reset 3602.115s 0.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 64.310us 1 1 100.00
aes_config_error 2.000s 234.632us 1 1 100.00
aes_alert_reset 3602.115s 0.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 557.876us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 348.575us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 3602.115s 0.000us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 243.185us 1 1 100.00
aes_sideload 3.000s 68.735us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 365.251us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 2.000s 101.765us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 67.125us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 255.114us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 255.114us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 77.945us 1 1 100.00
aes_csr_rw 2.000s 415.241us 1 1 100.00
aes_csr_aliasing 2.000s 231.564us 1 1 100.00
aes_same_csr_outstanding 2.000s 87.284us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 77.945us 1 1 100.00
aes_csr_rw 2.000s 415.241us 1 1 100.00
aes_csr_aliasing 2.000s 231.564us 1 1 100.00
aes_same_csr_outstanding 2.000s 87.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 34.867us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 3.000s 146.262us 0 1 0.00
aes_control_fi 28.000s 10004.044us 0 1 0.00
aes_cipher_fi 2.000s 54.876us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 116.406us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 116.406us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 116.406us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 116.406us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 346.981us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 3112.610us 1 1 100.00
aes_tl_intg_err 3.000s 187.820us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 187.820us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 3602.115s 0.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 116.406us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 116.406us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 1.000s 60.900us 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
aes_alert_reset 3602.115s 0.000us 0 1 0.00
aes_core_fi 1.000s 61.795us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 234.632us 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
aes_core_fi 1.000s 61.795us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 116.406us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 65.122us 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 243.185us 1 1 100.00
aes_sideload 3.000s 68.735us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 65.122us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 65.122us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 65.122us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 65.122us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 65.122us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 243.185us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 146.262us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 146.262us 0 1 0.00
aes_control_fi 28.000s 10004.044us 0 1 0.00
aes_cipher_fi 2.000s 54.876us 1 1 100.00
aes_ctr_fi 2.000s 51.209us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 146.262us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 146.262us 0 1 0.00
aes_control_fi 28.000s 10004.044us 0 1 0.00
aes_cipher_fi 2.000s 54.876us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 54.876us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 146.262us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 3.000s 146.262us 0 1 0.00
aes_control_fi 28.000s 10004.044us 0 1 0.00
aes_ctr_fi 2.000s 51.209us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 146.262us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 146.262us 0 1 0.00
aes_control_fi 28.000s 10004.044us 0 1 0.00
aes_cipher_fi 2.000s 54.876us 1 1 100.00
aes_ctr_fi 2.000s 51.209us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 3602.115s 0.000us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 146.262us 0 1 0.00
aes_control_fi 28.000s 10004.044us 0 1 0.00
aes_cipher_fi 2.000s 54.876us 1 1 100.00
aes_ctr_fi 2.000s 51.209us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 146.262us 0 1 0.00
aes_control_fi 28.000s 10004.044us 0 1 0.00
aes_cipher_fi 2.000s 54.876us 1 1 100.00
aes_ctr_fi 2.000s 51.209us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 3.000s 146.262us 0 1 0.00
aes_control_fi 28.000s 10004.044us 0 1 0.00
aes_ctr_fi 2.000s 51.209us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 146.262us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 146.262us 0 1 0.00
aes_control_fi 28.000s 10004.044us 0 1 0.00
aes_cipher_fi 2.000s 54.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 94.927us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 21881917493103953889533674900480365181838156077990962354130551725522309167749 1091
UVM_INFO @ 34867242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 92915361153398236855795708903775805656177306714989402148147317793906512878617 3561
UVM_INFO @ 101765467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_alert_reset 78184649224375446034158185327372244881698430141153842490829689544640800413234 None
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 18825824873123570289400545256512122794158076462861926544163145442040022078679 5116
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 18128523076236554030407107169013639919474331355629279985862900004329509121376 146
UVM_INFO @ 10004043899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:104) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 83561522093499458269774311215864376961412397663182609849924898492050070360670 112
UVM_INFO @ 94927019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---