Simulation Results: alert_handler

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.29 %
  • code
  • 90.55 %
  • assert
  • 98.20 %
  • func
  • 79.11 %
  • line
  • 99.72 %
  • branch
  • 98.31 %
  • cond
  • 90.23 %
  • toggle
  • 88.68 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 53.210s 1370.627us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 2.990s 25.001us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.250s 31.802us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 229.080s 20845.370us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 97.900s 4855.874us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.400s 324.838us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.250s 31.802us 1 1 100.00
alert_handler_csr_aliasing 97.900s 4855.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 251.850s 28832.557us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 32.840s 8515.498us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1435.880s 239572.664us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 37.400s 3431.129us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 53.210s 1370.627us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 12.700s 2567.536us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 44.380s 1089.854us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 313.960s 52843.368us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 2885.440s 94031.622us 1 1 100.00
alert_handler_lpg_stub_clk 1602.000s 37948.823us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1473.210s 77893.422us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 8.940s 262.756us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.140s 62.022us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.190s 18.909us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 2.880s 78.476us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 2.880s 78.476us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 2.990s 25.001us 1 1 100.00
alert_handler_csr_rw 3.250s 31.802us 1 1 100.00
alert_handler_csr_aliasing 97.900s 4855.874us 1 1 100.00
alert_handler_same_csr_outstanding 30.850s 2591.861us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 2.990s 25.001us 1 1 100.00
alert_handler_csr_rw 3.250s 31.802us 1 1 100.00
alert_handler_csr_aliasing 97.900s 4855.874us 1 1 100.00
alert_handler_same_csr_outstanding 30.850s 2591.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 70.250s 3285.456us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 70.250s 3285.456us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 70.250s 3285.456us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 70.250s 3285.456us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 955.170s 16832.928us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
alert_handler_tl_intg_err 2.920s 52.412us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.920s 52.412us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 70.250s 3285.456us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 53.210s 1370.627us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 53.210s 1370.627us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 53.210s 1370.627us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 53.210s 1370.627us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 37.400s 3431.129us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2885.440s 94031.622us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 37.400s 3431.129us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1435.880s 239572.664us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1435.880s 239572.664us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.290s 366.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 5.720s 223.259us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 36533575611732784867687399928427653262331675686941462944120985036457372358185 180
UVM_INFO @ 262755901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 30358007415895539927993378301692563238034280755529438644323971167553868275757 83
UVM_INFO @ 223258901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---