Simulation Results: clkmgr

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.47 %
  • code
  • 68.60 %
  • assert
  • 88.64 %
  • func
  • 60.16 %
  • line
  • 81.71 %
  • branch
  • 86.53 %
  • cond
  • 78.25 %
  • toggle
  • 96.51 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
61.54%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.040s 19.178us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.770s 17.617us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.640s 3.023us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.620s 152.062us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.110s 17.645us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.020s 41.457us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.640s 3.023us 0 1 0.00
clkmgr_csr_aliasing 1.110s 17.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.840s 31.099us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.230s 33.696us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.050s 14.620us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.040s 19.178us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.800s 8.147us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.710s 4.945us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.800s 8.147us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.820s 16.845us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.770s 14.936us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 6.820s 506.530us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 6.820s 506.530us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.770s 17.617us 1 1 100.00
clkmgr_csr_rw 0.640s 3.023us 0 1 0.00
clkmgr_csr_aliasing 1.110s 17.645us 1 1 100.00
clkmgr_same_csr_outstanding 0.830s 8.672us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.770s 17.617us 1 1 100.00
clkmgr_csr_rw 0.640s 3.023us 0 1 0.00
clkmgr_csr_aliasing 1.110s 17.645us 1 1 100.00
clkmgr_same_csr_outstanding 0.830s 8.672us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 95.690s 10014.617us 0 1 0.00
clkmgr_tl_intg_err 0.810s 22.045us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 70.962us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 70.962us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 70.962us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 70.962us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.800s 3.502us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.810s 22.045us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.800s 8.147us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.710s 4.945us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.350s 70.962us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.780s 15.569us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.640s 3.023us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 95.690s 10014.617us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 3.023us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.640s 3.023us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 95.690s 10014.617us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.690s 10.533us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.870s 27.952us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 41767166604099587041843214704660861291362275543543542797954426224804926699574 75
UVM_INFO @ 3502184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 55971965939601435579672361959647880003850011931621329919518631591067204783910 85
UVM_INFO @ 22044713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 38935099983369174309260841734124864708913772536507158046656609830544909394483 75
UVM_INFO @ 3023180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 14409926774959666271178424340392218872366819505430807565006528311724864730896 75
UVM_INFO @ 8147197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 23299743649554715725603660339633380103341747073966495746890502216005540895908 75
UVM_INFO @ 16844521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 100114591116150546693266693814359470401129339276436165971221276965635567470636 77
UVM_INFO @ 4945145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 91604308487299220635946167915325552674416657559622845117062555201593911442700 79
UVM_INFO @ 27951596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 57074943224946729863760639074688960012950176432589388272765394951227411828680 74
UVM_INFO @ 10533038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 87674557896049637195152324359450984332050949602664169447419443297424601453129 86
UVM_INFO @ 10014617312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 19864983165685617669274838060001142448076946792626835981443301575818058639854 75
UVM_INFO @ 152061935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 43929151996459623670169155163121972543428014905688603537002032549470287239205 75
UVM_INFO @ 8671614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---