Simulation Results: csrng

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 77.68 %
  • code
  • 91.58 %
  • assert
  • 94.32 %
  • func
  • 47.13 %
  • block
  • 95.15 %
  • line
  • 95.81 %
  • branch
  • 88.39 %
  • toggle
  • 86.88 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 6.000s 392.530us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 35.648us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 48.214us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 21.000s 880.968us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 38.524us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 67.714us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 48.214us 1 1 100.00
csrng_csr_aliasing 2.000s 38.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 270.653us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 40.874us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 40.874us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 3.000s 101.249us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 16.567us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 20.697us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 113.682us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 113.682us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 35.648us 1 1 100.00
csrng_csr_rw 2.000s 48.214us 1 1 100.00
csrng_csr_aliasing 2.000s 38.524us 1 1 100.00
csrng_same_csr_outstanding 2.000s 36.579us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 35.648us 1 1 100.00
csrng_csr_rw 2.000s 48.214us 1 1 100.00
csrng_csr_aliasing 2.000s 38.524us 1 1 100.00
csrng_same_csr_outstanding 2.000s 36.579us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 60.380us 1 1 100.00
csrng_tl_intg_err 5.000s 137.969us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 37.175us 1 1 100.00
csrng_csr_rw 2.000s 48.214us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 270.653us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 3.000s 101.249us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
csrng_sec_cm 2.000s 60.380us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
csrng_sec_cm 2.000s 60.380us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
csrng_sec_cm 2.000s 60.380us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
csrng_sec_cm 2.000s 60.380us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
csrng_sec_cm 2.000s 60.380us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 270.653us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 3.000s 101.249us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 270.653us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 137.969us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
csrng_sec_cm 2.000s 60.380us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
csrng_sec_cm 2.000s 60.380us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 10.000s 830.689us 1 1 100.00
csrng_err 2.000s 22.623us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 6.000s 93.995us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 74295389796303545035520834368084714445604187751855348357795825091631879914854 100
UVM_INFO @ 40873604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 63267805085591917132924774644093451251801479801537789110291278015832417307411 108
UVM_INFO @ 93995286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---