Simulation Results: edn/edn1

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.31 %
  • code
  • 83.54 %
  • assert
  • 97.66 %
  • func
  • 77.73 %
  • line
  • 97.72 %
  • branch
  • 92.21 %
  • cond
  • 87.77 %
  • toggle
  • 95.70 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 18.895us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 40.285us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 16.885us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.590s 310.227us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.210s 137.992us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.830s 18.600us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 16.885us 1 1 100.00
edn_csr_aliasing 1.210s 137.992us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.870s 71.448us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.870s 71.448us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.870s 71.448us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.060s 23.277us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.150s 266.936us 1 1 100.00
errs 1 1 100.00
edn_err 0.770s 36.790us 1 1 100.00
disable 2 2 100.00
edn_disable 0.930s 14.852us 1 1 100.00
edn_disable_auto_req_mode 1.210s 48.444us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.370s 561.426us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 25.334us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.740s 24.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.320s 254.750us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.320s 254.750us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 40.285us 1 1 100.00
edn_csr_rw 0.760s 16.885us 1 1 100.00
edn_csr_aliasing 1.210s 137.992us 1 1 100.00
edn_same_csr_outstanding 0.950s 19.982us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 40.285us 1 1 100.00
edn_csr_rw 0.760s 16.885us 1 1 100.00
edn_csr_aliasing 1.210s 137.992us 1 1 100.00
edn_same_csr_outstanding 0.950s 19.982us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.050s 1258.049us 1 1 100.00
edn_tl_intg_err 2.200s 1653.390us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.980s 21.186us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.150s 266.936us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.050s 1258.049us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.050s 1258.049us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.050s 1258.049us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.050s 1258.049us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.150s 266.936us 1 1 100.00
edn_sec_cm 3.050s 1258.049us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.150s 266.936us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.200s 1653.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 26.500s 1590.543us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 46211563422556232904822688029394379125810674185929312846015996222745501293149 205
UVM_INFO @ 1590543122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---