Simulation Results: entropy_src/rng_16bits

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 70.61 %
  • code
  • 82.55 %
  • assert
  • 74.20 %
  • func
  • 55.09 %
  • block
  • 94.15 %
  • line
  • 97.84 %
  • branch
  • 86.15 %
  • toggle
  • 51.42 %
  • FSM
  • 94.79 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 26.597us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 19.841us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 77.326us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 8.000s 1841.548us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 5.000s 738.371us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 12.913us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 77.326us 1 1 100.00
entropy_src_csr_aliasing 5.000s 738.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 26.597us 1 1 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
entropy_src_fw_ov 170.000s 13146.956us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 170.000s 13146.956us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 215.000s 14037.426us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
entropy_src_intr 20.000s 797.769us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
entropy_src_functional_alerts 5.000s 190.687us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 310.000s 14212.651us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 122.322us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 40.000s 5393.771us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 15.345us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 99.046us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 504.230us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 504.230us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 19.841us 1 1 100.00
entropy_src_csr_rw 1.000s 77.326us 1 1 100.00
entropy_src_csr_aliasing 5.000s 738.371us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 135.719us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 19.841us 1 1 100.00
entropy_src_csr_rw 1.000s 77.326us 1 1 100.00
entropy_src_csr_aliasing 5.000s 738.371us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 135.719us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 57.481us 1 1 100.00
entropy_src_tl_intg_err 4.000s 122.698us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
entropy_src_cfg_regwen 1.000s 64.517us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
entropy_src_fw_ov 170.000s 13146.956us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 122.322us 1 1 100.00
entropy_src_sec_cm 2.000s 57.481us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 122.322us 1 1 100.00
entropy_src_sec_cm 2.000s 57.481us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 67.000s 13102.516us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 122.322us 1 1 100.00
entropy_src_sec_cm 2.000s 57.481us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 122.322us 1 1 100.00
entropy_src_sec_cm 2.000s 57.481us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 122.322us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 190.687us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 122.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 56.000s 14078.756us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 12.000s 413.687us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 104418999132273210311397043013183627660986006219486010912442661995702961765211 828
UVM_INFO @ 413687138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror repcnts_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 95882328960166498257223367132707748039877216921338917529959319576691960971810 113
UVM_INFO @ 12913242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---