Simulation Results: hmac

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.91 %
  • code
  • 95.22 %
  • assert
  • 97.17 %
  • func
  • 29.35 %
  • block
  • 97.14 %
  • line
  • 97.99 %
  • branch
  • 92.82 %
  • toggle
  • 96.96 %
  • FSM
  • 93.10 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.000s 1478.342us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 86.742us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 35.281us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 683.170us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.000s 2446.105us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 185.000s 25255.118us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 35.281us 1 1 100.00
hmac_csr_aliasing 7.000s 2446.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 8.000s 359.292us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 17.000s 2264.923us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 209.000s 66046.643us 1 1 100.00
hmac_test_sha384_vectors 26.000s 1630.469us 1 1 100.00
hmac_test_sha512_vectors 22.000s 302.053us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 475.394us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 394.233us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 1190.785us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.000s 1690.780us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 131.000s 4066.555us 1 1 100.00
error 1 1 100.00
hmac_error 44.000s 16643.935us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 80.000s 8815.898us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.000s 1478.342us 1 1 100.00
hmac_long_msg 8.000s 359.292us 1 1 100.00
hmac_back_pressure 17.000s 2264.923us 1 1 100.00
hmac_datapath_stress 131.000s 4066.555us 1 1 100.00
hmac_burst_wr 12.000s 1690.780us 1 1 100.00
hmac_stress_all 36.000s 8632.464us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.000s 1478.342us 1 1 100.00
hmac_long_msg 8.000s 359.292us 1 1 100.00
hmac_back_pressure 17.000s 2264.923us 1 1 100.00
hmac_datapath_stress 131.000s 4066.555us 1 1 100.00
hmac_wipe_secret 80.000s 8815.898us 1 1 100.00
hmac_test_sha256_vectors 209.000s 66046.643us 1 1 100.00
hmac_test_sha384_vectors 26.000s 1630.469us 1 1 100.00
hmac_test_sha512_vectors 22.000s 302.053us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 475.394us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 394.233us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 1190.785us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.000s 1478.342us 1 1 100.00
hmac_long_msg 8.000s 359.292us 1 1 100.00
hmac_back_pressure 17.000s 2264.923us 1 1 100.00
hmac_datapath_stress 131.000s 4066.555us 1 1 100.00
hmac_burst_wr 12.000s 1690.780us 1 1 100.00
hmac_error 44.000s 16643.935us 1 1 100.00
hmac_wipe_secret 80.000s 8815.898us 1 1 100.00
hmac_test_sha256_vectors 209.000s 66046.643us 1 1 100.00
hmac_test_sha384_vectors 26.000s 1630.469us 1 1 100.00
hmac_test_sha512_vectors 22.000s 302.053us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 475.394us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 394.233us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 1190.785us 1 1 100.00
hmac_stress_all 36.000s 8632.464us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 36.000s 8632.464us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 16.606us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 45.790us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 205.962us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 205.962us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 86.742us 1 1 100.00
hmac_csr_rw 2.000s 35.281us 1 1 100.00
hmac_csr_aliasing 7.000s 2446.105us 1 1 100.00
hmac_same_csr_outstanding 2.000s 39.165us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 86.742us 1 1 100.00
hmac_csr_rw 2.000s 35.281us 1 1 100.00
hmac_csr_aliasing 7.000s 2446.105us 1 1 100.00
hmac_same_csr_outstanding 2.000s 39.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 88.786us 1 1 100.00
hmac_tl_intg_err 2.000s 178.640us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 178.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.000s 1478.342us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 171.053us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 55.000s 4694.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 9.762us 1 1 100.00