Simulation Results

Simulation Results: i2c

14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.90 %

code
85.69 %

assert
97.46 %

func
80.56 %

block
95.95 %

line
95.37 %

branch
92.74 %

toggle
72.64 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	309.000s	2519.747us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	11.000s	2376.149us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	20.095us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	91.316us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	6.000s	2375.112us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	658.338us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	26.813us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	91.316us	1	1	100.00
	i2c_csr_aliasing	2.000s	658.338us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	2.000s	296.172us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	64.000s	4773.072us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	5.000s	489.198us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	45.869us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1654.000s	10646.244us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	257.448us	1	1	100.00
	i2c_host_fifo_fmt_empty	58.000s	399.345us	1	1	100.00
	i2c_host_fifo_reset_rx	2.000s	525.339us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	249.000s	2635.075us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	25.000s	9752.903us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	5.966us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	452.181us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	845.000s	48707.309us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	6.000s	645.300us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	24.000s	1138.121us	1	1	100.00
	i2c_target_intr_smoke	6.000s	1420.876us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	258.516us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	404.610us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	28.000s	21387.874us	1	1	100.00
	i2c_target_stress_rd	24.000s	1138.121us	1	1	100.00
	i2c_target_intr_stress_wr	607.000s	4038.499us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.000s	1357.460us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	2.000s	255.034us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	8.000s	11953.961us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	8.000s	10507.070us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	2139.876us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	490.736us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	5.000s	489.198us	1	1	100.00
	i2c_host_perf_precise	57.000s	2424.751us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	25.000s	9752.903us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.000s	76.633us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	3.000s	1794.350us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	539.821us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	512.897us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	11.000s	398.291us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	479.775us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	41.305us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	15.903us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	4.000s	457.027us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	4.000s	457.027us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	20.095us	1	1	100.00
	i2c_csr_rw	1.000s	91.316us	1	1	100.00
	i2c_csr_aliasing	2.000s	658.338us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	58.118us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	20.095us	1	1	100.00
	i2c_csr_rw	1.000s	91.316us	1	1	100.00
	i2c_csr_aliasing	2.000s	658.338us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	58.118us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	6.000s	277.360us	1	1	100.00
	i2c_sec_cm	1.000s	276.290us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	6.000s	277.360us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	17.000s	987.726us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	98.046us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	19.000s	3902.309us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_stress_all	27131144290082393684452835889605787057829657401174219688888398697352987021135	119	UVM_INFO @ 4773072202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	32085315480028133524193797322389216863719309206721440283482100829367604078348	110	UVM_INFO @ 3902309262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	106199214823820415233567056629886549079743884583704714633007725746777966395866	90	UVM_INFO @ 5965824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	i2c_host_fifo_watermark	90851483927534021028342310693557442546413511155261967633555379213613039108844	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	1287825864286196443364009093224318774378010752818799987476640677534921704722	93	UVM_INFO @ 452181442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	77301439292983805373452159857600825395915526509459953578329154320734886334810	87	UVM_INFO @ 98045577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!				1 test run
	i2c_target_stress_all	86848429795017453717102279743384107253830247367857337532688441131713086008635	98	UVM_INFO @ 48707308649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	15561979193751773665227247168362139218976082060422700441906268360937695937675	88	UVM_INFO @ 10507070012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	11190137289412386471182782680442295718406826081616490677840842372341735447449	99	UVM_INFO @ 987726280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---