Simulation Results: kmac/masked

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.72 %
  • code
  • 68.63 %
  • assert
  • 96.77 %
  • func
  • 76.76 %
  • line
  • 95.43 %
  • branch
  • 89.63 %
  • cond
  • 84.65 %
  • toggle
  • 29.14 %
  • FSM
  • 44.30 %
Validation stages
V1
100.00%
V2
75.86%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 70.120s 19033.575us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.180s 60.170us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.910s 20.511us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 10.020s 937.001us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 8.340s 2550.980us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.450s 92.860us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.910s 20.511us 1 1 100.00
kmac_csr_aliasing 8.340s 2550.980us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.830s 49.772us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.070s 28.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 765.750s 35936.664us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 953.130s 135896.104us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 26.410s 2331.399us 1 1 100.00
kmac_test_vectors_sha3_256 2346.580s 111698.963us 1 1 100.00
kmac_test_vectors_sha3_384 21.840s 2002.401us 1 1 100.00
kmac_test_vectors_sha3_512 857.210s 14038.720us 1 1 100.00
kmac_test_vectors_shake_128 198.340s 18134.134us 1 1 100.00
kmac_test_vectors_shake_256 291.920s 250506.365us 1 1 100.00
kmac_test_vectors_kmac 3.640s 856.649us 1 1 100.00
kmac_test_vectors_kmac_xof 2.290s 830.392us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 126.690s 7661.982us 1 1 100.00
app 0 1 0.00
kmac_app 5.780s 570.012us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.450s 129.093us 0 1 0.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 12.770s 3097.088us 1 1 100.00
error 0 1 0.00
kmac_error 36.790s 2585.056us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.190s 48.985us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.830s 28.250us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 20.060s 399.871us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.870s 21.791us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.400s 192.855us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.720s 79.139us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 11.070s 1833.629us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.940s 14.678us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.940s 77.422us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.460s 136.192us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.460s 136.192us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.180s 60.170us 1 1 100.00
kmac_csr_rw 0.910s 20.511us 1 1 100.00
kmac_csr_aliasing 8.340s 2550.980us 1 1 100.00
kmac_same_csr_outstanding 1.520s 27.539us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.180s 60.170us 1 1 100.00
kmac_csr_rw 0.910s 20.511us 1 1 100.00
kmac_csr_aliasing 8.340s 2550.980us 1 1 100.00
kmac_same_csr_outstanding 1.520s 27.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 2.050s 101.360us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 2.050s 101.360us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 2.050s 101.360us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 2.050s 101.360us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.450s 375.338us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 79.730s 9382.530us 1 1 100.00
kmac_tl_intg_err 5.590s 224.059us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 5.590s 224.059us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.720s 79.139us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 70.120s 19033.575us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 126.690s 7661.982us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 2.050s 101.360us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 79.730s 9382.530us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 79.730s 9382.530us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 79.730s 9382.530us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 70.120s 19033.575us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.720s 79.139us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 79.730s 9382.530us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 9.590s 152.131us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 70.120s 19033.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 65.910s 32704.050us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 5 test runs
kmac_app 97783411846395154592293342089065474425860227859407974115384289928807564019837 79
UVM_INFO @ 570011898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 74309063557534734848931921328306442226124149901984375600236331849349086202494 77
UVM_INFO @ 129093436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 10423709808762860650444663715782287907522213748382281394498130997940747312034 94
UVM_INFO @ 2585056245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 61606797734316956944319867386176036187502768187228975703404500369744962461861 77
UVM_INFO @ 192854537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 38868888133356224492691841884466967165289371283353137918597529803329054299173 84
UVM_INFO @ 1833628953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_sideload_invalid 44723445582146037651204367222794888974054296635675211509291670979318839042881 82
UVM_ERROR @ 28249532 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 28249532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 33534225215725151265913606935243614309530423210355842668351711189288789130806 78
UVM_ERROR @ 48984942 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 48984942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 1 test run
kmac_mubi 84345034219333317035935097672663245735375848496852865690892893217502532095911 81
UVM_INFO @ 152130642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 104049219700971428265395804986157744155581320269991077784441852226132298688376 201
UVM_INFO @ 32704049723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---