Simulation Results: lc_ctrl/volatile_unlock_disabled

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.07 %
  • code
  • 92.76 %
  • assert
  • 96.83 %
  • func
  • 86.62 %
  • block
  • 96.48 %
  • line
  • 97.20 %
  • branch
  • 91.03 %
  • toggle
  • 87.58 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 121.354us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 34.495us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 61.200us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 4.000s 449.667us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 141.290us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 46.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 61.200us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 141.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 8.000s 391.522us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 2118.613us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 41.099us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 95.428us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 344.840us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_ctrl_prog_failure 2.000s 95.428us 1 1 100.00
lc_ctrl_errors 5.000s 344.840us 1 1 100.00
lc_ctrl_security_escalation 5.000s 515.405us 1 1 100.00
lc_ctrl_jtag_state_failure 10.000s 4230.535us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 329.835us 1 1 100.00
lc_ctrl_jtag_errors 36.000s 12977.526us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 118.637us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 5222.054us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 329.835us 1 1 100.00
lc_ctrl_jtag_errors 36.000s 12977.526us 1 1 100.00
lc_ctrl_jtag_access 11.000s 2836.866us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 2115.436us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 102.042us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 60.529us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 1669.402us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 532.339us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 39.700us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 130.016us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 125.386us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 15.000s 2605.598us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 13.276us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 131.000s 58610.186us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 93.570us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 368.980us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 368.980us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 34.495us 1 1 100.00
lc_ctrl_csr_rw 1.000s 61.200us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 141.290us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 58.893us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 34.495us 1 1 100.00
lc_ctrl_csr_rw 1.000s 61.200us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 141.290us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 58.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.000s 330.923us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 87.232us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 87.232us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 2118.613us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_ctrl_sec_cm 7.000s 330.923us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_ctrl_sec_cm 7.000s 330.923us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_ctrl_sec_cm 7.000s 330.923us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_ctrl_sec_cm 7.000s 330.923us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_ctrl_sec_cm 7.000s 330.923us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_ctrl_sec_cm 7.000s 330.923us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_ctrl_sec_cm 7.000s 330.923us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 336.774us 1 1 100.00
lc_ctrl_sec_cm 7.000s 330.923us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 515.405us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 8.000s 391.522us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 5222.054us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 2098.483us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 2098.483us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 461.586us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1915.555us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1915.555us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 47.000s 4672.143us 1 1 100.00