Simulation Results: lc_ctrl/volatile_unlock_enabled

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.18 %
  • code
  • 93.23 %
  • assert
  • 96.69 %
  • func
  • 86.62 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 87.31 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 137.670us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 21.643us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 63.022us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 39.776us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 68.161us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 79.589us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 63.022us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 68.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 102.804us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 311.055us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.996us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 96.310us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 3043.035us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_ctrl_prog_failure 3.000s 96.310us 1 1 100.00
lc_ctrl_errors 6.000s 3043.035us 1 1 100.00
lc_ctrl_security_escalation 8.000s 1610.156us 1 1 100.00
lc_ctrl_jtag_state_failure 10.000s 1098.391us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 88.053us 1 1 100.00
lc_ctrl_jtag_errors 55.000s 13857.321us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 8.000s 455.800us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 4274.153us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 88.053us 1 1 100.00
lc_ctrl_jtag_errors 55.000s 13857.321us 1 1 100.00
lc_ctrl_jtag_access 5.000s 2334.101us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 946.984us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 207.052us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 158.974us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 6593.476us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.000s 2797.097us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 44.749us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 97.593us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 29.412us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 14.000s 2513.945us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 45.981us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 31.000s 9001.849us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 19.259us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 28.111us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 28.111us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 21.643us 1 1 100.00
lc_ctrl_csr_rw 1.000s 63.022us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 68.161us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 92.838us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 21.643us 1 1 100.00
lc_ctrl_csr_rw 1.000s 63.022us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 68.161us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 92.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 518.720us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 135.322us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 135.322us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 311.055us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_ctrl_sec_cm 2.000s 518.720us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_ctrl_sec_cm 2.000s 518.720us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_ctrl_sec_cm 2.000s 518.720us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_ctrl_sec_cm 2.000s 518.720us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_ctrl_sec_cm 2.000s 518.720us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_ctrl_sec_cm 2.000s 518.720us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_ctrl_sec_cm 2.000s 518.720us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 1012.894us 1 1 100.00
lc_ctrl_sec_cm 2.000s 518.720us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.000s 1610.156us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 102.804us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 4274.153us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 643.593us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 643.593us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 335.676us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 332.408us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 332.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 18.000s 2852.158us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 64696952686019101585637008171431384051065066686334834476008054611360244684350 5706
UVM_INFO @ 2852157546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---