Simulation Results: otbn

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.04 %
  • code
  • 85.15 %
  • assert
  • 87.89 %
  • func
  • 94.07 %
  • block
  • 99.25 %
  • line
  • 99.44 %
  • branch
  • 94.75 %
  • toggle
  • 83.04 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 42.906us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 22.381us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 55.763us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 22.952us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 434.096us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 41.683us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 84.564us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 22.952us 1 1 100.00
otbn_csr_aliasing 4.000s 41.683us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 36.000s 765.871us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 37.000s 11374.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 37.000s 355.310us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 64.000s 169.164us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 280.000s 3030.693us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 21.000s 164.473us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 29.739us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 63.351us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 14.000s 63.622us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 41.669us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 25.551us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 142.222us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 142.222us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 55.763us 1 1 100.00
otbn_csr_rw 4.000s 22.952us 1 1 100.00
otbn_csr_aliasing 4.000s 41.683us 1 1 100.00
otbn_same_csr_outstanding 5.000s 51.124us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 55.763us 1 1 100.00
otbn_csr_rw 4.000s 22.952us 1 1 100.00
otbn_csr_aliasing 4.000s 41.683us 1 1 100.00
otbn_same_csr_outstanding 5.000s 51.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 43.695us 1 1 100.00
otbn_dmem_err 12.000s 35.216us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 10.000s 99.656us 1 1 100.00
otbn_controller_ispr_rdata_err 16.000s 58.328us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 17.198us 1 1 100.00
otbn_urnd_err 7.000s 49.604us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.903us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 81.953us 1 1 100.00
otbn_non_sec_partial_wipe 0 1 0.00
otbn_partial_wipe 5.000s 17.756us 0 1 0.00
tl_intg_err 1 2 50.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
otbn_tl_intg_err 19.000s 1642.136us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 29.000s 186.018us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 42.906us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 12.000s 35.216us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 43.695us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 19.000s 1642.136us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 29.739us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 43.695us 1 1 100.00
otbn_dmem_err 12.000s 35.216us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 63.351us 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.903us 1 1 100.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 22.381us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 43.695us 1 1 100.00
otbn_dmem_err 12.000s 35.216us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 63.351us 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.903us 1 1 100.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 29.739us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 43.695us 1 1 100.00
otbn_dmem_err 12.000s 35.216us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 63.351us 1 1 100.00
otbn_illegal_mem_acc 6.000s 17.903us 1 1 100.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 22.381us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 29.333us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 24.160us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 23.000s 239.499us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 23.000s 239.499us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 49.193us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 238.275us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 12.956us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 12.956us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 10.249us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 22.381us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 22.381us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 22.381us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 280.000s 3030.693us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 22.381us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 22.381us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 11.000s 141.205us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 22.381us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 19.000s 248.094us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 436.000s 3385.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 9.000s 26.511us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_partial_wipe 96072885436477477972333626166428685612678532510979730310584797280076086092859 114
UVM_INFO @ 17756292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 20224832439701628255803499208062648006121233230466681193877219198800003390895 129
UVM_ERROR @ 248093730 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 248093730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---