Simulation Results: otp_ctrl

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.60 %
  • code
  • 72.41 %
  • assert
  • 93.94 %
  • func
  • 54.44 %
  • line
  • 87.49 %
  • branch
  • 84.09 %
  • cond
  • 85.86 %
  • toggle
  • 66.94 %
  • FSM
  • 37.67 %
Validation stages
V1
100.00%
V2
65.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.720s 831.488us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.270s 431.664us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.140s 163.177us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.830s 190.956us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.990s 1063.051us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 8.700s 371.356us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.160s 1759.230us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.830s 190.956us 1 1 100.00
otp_ctrl_csr_aliasing 8.700s 371.356us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.330s 42.994us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.260s 632.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 135.860s 28149.398us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.270s 2474.181us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 18.080s 1100.787us 0 1 0.00
otp_ctrl_check_fail 5.300s 332.832us 1 1 100.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 2.840s 83.910us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 7.090s 943.222us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 6.170s 678.992us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 10.870s 1340.943us 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 32.580s 15067.215us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 20.780s 2055.706us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 17.240s 1225.867us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 14.290s 1783.616us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.230s 96.598us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.030s 262.821us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.240s 361.919us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.240s 361.919us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.140s 163.177us 1 1 100.00
otp_ctrl_csr_rw 1.830s 190.956us 1 1 100.00
otp_ctrl_csr_aliasing 8.700s 371.356us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.280s 583.531us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.140s 163.177us 1 1 100.00
otp_ctrl_csr_rw 1.830s 190.956us 1 1 100.00
otp_ctrl_csr_aliasing 8.700s 371.356us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.280s 583.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
otp_ctrl_tl_intg_err 11.350s 730.154us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.350s 730.154us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.270s 431.664us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.270s 431.664us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
otp_ctrl_macro_errs 20.780s 2055.706us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
otp_ctrl_macro_errs 20.780s 2055.706us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.690s 279.636us 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.270s 2474.181us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 5.300s 332.832us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 7.090s 943.222us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 7.090s 943.222us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 7.090s 943.222us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 7.090s 943.222us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 7.090s 943.222us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.270s 431.664us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 7.090s 943.222us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.270s 431.664us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 300.900s 20319.223us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 2.840s 83.910us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.270s 431.664us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.270s 431.664us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 20.780s 2055.706us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 90.770s 69093.532us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 50.000s 15113.261us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 3 test runs
otp_ctrl_dai_lock 35788662171861729090377697738074806849625182052290491606162278368623313326159 7659
UVM_INFO @ 943222386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 13636039751247649712881720521871709334676492860779859655958401230006014154248 6247
UVM_INFO @ 678991600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55246595934277990662903871480359783986780496647728176244118414662454469340340 3870
UVM_INFO @ 15113260617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 47847822730744053819779801056791523100612297541281843855933512738811104625153 112839
UVM_INFO @ 28149398176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 30668999497334337968046116180961023074988155456211090436185390175379290726487 89
UVM_INFO @ 69093532463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_background_chks 89675481650445627357998862766917460768842791091716885198988937581305067848307 25300
UVM_INFO @ 1100786873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 52301797298684936348279372308236443581332497646222723721212716125607989894246 8686
UVM_INFO @ 2055705739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 89751290943793105669211833500811544808255650109328436449269002402302466795659 2138
UVM_INFO @ 83910421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_stress_all 83894502697488568391234954570850835786041379034991894396582338491464711344333 18402
UVM_INFO @ 1783616102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---