Simulation Results: rom_ctrl/32kb

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.63 %
  • code
  • 92.51 %
  • assert
  • 97.67 %
  • func
  • 96.71 %
  • block
  • 96.15 %
  • line
  • 96.58 %
  • branch
  • 93.55 %
  • toggle
  • 84.66 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 313.551us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 148.348us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 214.881us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 209.830us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 537.360us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 427.826us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 214.881us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 537.360us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 794.168us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 174.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 322.241us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.000s 759.890us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.000s 536.435us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 924.075us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 318.392us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 318.392us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 148.348us 1 1 100.00
rom_ctrl_csr_rw 2.000s 214.881us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 537.360us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 126.950us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 148.348us 1 1 100.00
rom_ctrl_csr_rw 2.000s 214.881us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 537.360us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 126.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.000s 1942.996us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 54.000s 2012.463us 1 1 100.00
rom_ctrl_tl_intg_err 25.000s 595.052us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 54.000s 2012.463us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 54.000s 2012.463us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 54.000s 2012.463us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 54.000s 2012.463us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 313.551us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 313.551us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 313.551us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 25.000s 595.052us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
rom_ctrl_kmac_err_chk 6.000s 536.435us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.000s 2901.560us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.000s 1942.996us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 54.000s 2012.463us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 10.000s 456.908us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 88800297851484912440798079757956378552715512524273168012728359755389145776646 88
UVM_INFO @ 322241348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---