Simulation Results: rv_dm/use_dmi_interface

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.31 %
  • code
  • 81.28 %
  • assert
  • 96.74 %
  • func
  • 92.90 %
  • block
  • 92.24 %
  • line
  • 92.59 %
  • branch
  • 78.90 %
  • toggle
  • 73.26 %
  • FSM
  • 80.36 %
Validation stages
V1
96.30%
V2
73.91%
V2S
71.43%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 33.000s 5834.868us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 30.000s 265.281us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 30.000s 133.968us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 34.000s 4012.653us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 32.000s 430.054us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 31.000s 9039.953us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 32.000s 4831.640us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 41.000s 11992.520us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 57.000s 234986.108us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 31.000s 257.882us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 32.000s 187.619us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 32.000s 226.503us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 30.000s 205.698us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 33.000s 147.388us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 30.000s 162.510us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 31.000s 356.186us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 33.000s 568.765us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 31.000s 257.882us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 31.000s 278.149us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 31.000s 260.399us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 32.000s 226.503us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 32.000s 236.924us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 32.000s 299.767us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 34.000s 166.573us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 50.000s 4382.324us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 61.000s 6980.527us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 31.000s 167.954us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 61.000s 6980.527us 1 1 100.00
rv_dm_csr_rw 34.000s 166.573us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 32.000s 51.297us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 30.000s 96.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 33.000s 5834.868us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 32.000s 1066.413us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 35.000s 180.405us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 30.000s 175.318us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 34.000s 2160.945us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 32.000s 1117.009us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 31.000s 151.328us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 34.000s 6519.756us 0 1 0.00
sba_autoincrement 1 1 100.00
rv_dm_autoincr_sba_tl_access 35.000s 2245.823us 1 1 100.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 32.000s 523.185us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 36.000s 3268.397us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 30.000s 264.746us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 33.000s 54.134us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 35.000s 7630.083us 1 1 100.00
rv_dm_tap_fsm_rand_reset 58.000s 6120.219us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 30.000s 204.562us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 29.000s 621.648us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 29.000s 44.935us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 32.000s 156.438us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 32.000s 156.438us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 61.000s 6980.527us 1 1 100.00
rv_dm_csr_hw_reset 32.000s 299.767us 1 1 100.00
rv_dm_csr_rw 34.000s 166.573us 1 1 100.00
rv_dm_same_csr_outstanding 32.000s 173.444us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 61.000s 6980.527us 1 1 100.00
rv_dm_csr_hw_reset 32.000s 299.767us 1 1 100.00
rv_dm_csr_rw 34.000s 166.573us 1 1 100.00
rv_dm_same_csr_outstanding 32.000s 173.444us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 40.000s 1981.904us 1 1 100.00
rv_dm_tl_intg_err 43.000s 3434.844us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 43.000s 3434.844us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 36.000s 3268.397us 1 1 100.00
rv_dm_debug_disabled 30.000s 132.932us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 36.000s 3268.397us 1 1 100.00
rv_dm_debug_disabled 30.000s 132.932us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 33.000s 5834.868us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 33.000s 249.541us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 0 1 0.00
rv_dm_sparse_lc_gate_fsm 31.000s 113.021us 0 1 0.00
sec_cm_mem_tl_lc_gate_fsm_sparse 0 1 0.00
rv_dm_sparse_lc_gate_fsm 31.000s 113.021us 0 1 0.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 33.000s 249.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 49.000s 1516.256us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 32.000s 0.774us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 94163897599179486916485503019814535378768850890653855752604888070878972528047 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23810
rv_dm_bad_sba_tl_access 3798619446278619798935594117038530984121971320346692488309634816432753708633 108
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23885
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 2 test runs
rv_dm_jtag_dmi_debug_disabled 107796793502479240281780624903907354782520124434623038148983911659296024911378 87
UVM_INFO @ 523185332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 46820611964954484547376835907142488757211893948563545337727097128206596378211 89
UVM_INFO @ 621647643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 1 test run
rv_dm_delayed_resp_sba_tl_access 34771568511090266911258250201205542352278147402112963852444608504429855395801 107
UVM_INFO @ 151328090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 85883272657905773093715252489779954152903590000380274098555880085661375078635 87
UVM_INFO @ 205698202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 1 test run
rv_dm_hart_unavail 96257336251052730981952691100369219932018432019570631536651561097837735342713 87
UVM_INFO @ 54133876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_*/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed 1 test run
rv_dm_debug_disabled 22340689323923386222213132481005343505493195147468984966513738622937959139555 90
UVM_ERROR @ 132931780 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
UVM_INFO @ 132931780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
rv_dm_sparse_lc_gate_fsm 31407751278698571236769610646002706269342699397685215503012032694501224497776 87
UVM_INFO @ 113021336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_*/rtl/tlul_assert.sv,381): Assertion aKnown_AKnownEnable has failed 1 test run
rv_dm_scanmode 21795204606332939246479304893508154053582322775701579139614320193623583622076 87
UVM_ERROR @ 774146 ps: (tlul_assert.sv:381) [ASSERT FAILED] aKnown_AKnownEnable
UVM_INFO @ 774146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done) 1 test run
rv_dm_stress_all_with_rand_reset 3821323591650248661190511297698597431254779104023921502705458792119911347853 124
UVM_INFO @ 1516256215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---