Simulation Results: rv_timer

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.98 %
  • code
  • 95.85 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 203.139us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 15.780us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 17.693us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 179.212us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 25.179us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 125.205us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 17.693us 1 1 100.00
rv_timer_csr_aliasing 1.000s 25.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 134.854us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 1706.070us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 356.000s 1240271.287us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 356.000s 1240271.287us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.000s 4134.529us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 51.732us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 2.000s 19.240us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 1371.391us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 1371.391us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.780us 1 1 100.00
rv_timer_csr_rw 1.000s 17.693us 1 1 100.00
rv_timer_csr_aliasing 1.000s 25.179us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 146.504us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.780us 1 1 100.00
rv_timer_csr_rw 1.000s 17.693us 1 1 100.00
rv_timer_csr_aliasing 1.000s 25.179us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 146.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 392.601us 1 1 100.00
rv_timer_tl_intg_err 1.000s 386.024us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 386.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 242.418us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 48.484us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 40.000s 17684.331us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 84732456165337408518298661529602307489875945212529838313424962050054026643020 86
UVM_INFO @ 242417717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 15838790933855777834395527490747647097852346219046375490319562266697689564461 84
UVM_INFO @ 134853617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 2537889589810835034990833837887663189030285875483082532359895361059406513042 84
UVM_INFO @ 48484357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---