Simulation Results: spi_host

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.17 %
  • code
  • 91.14 %
  • assert
  • 94.14 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 64.000s 9452.842us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 19.430us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 19.910us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 281.195us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 24.102us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 26.625us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 19.910us 1 1 100.00
spi_host_csr_aliasing 1.000s 24.102us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 15.785us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 126.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 56.150us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 69.477us 1 1 100.00
spi_host_error_cmd 2.000s 18.307us 1 1 100.00
spi_host_event 9.000s 1606.084us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 594.805us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 594.805us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 594.805us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 145.000s 9167.759us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 14.000s 653.219us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 23.333us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 594.805us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 594.805us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 64.000s 9452.842us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 64.000s 9452.842us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 248.719us 1 1 100.00
spien 1 1 100.00
spi_host_spien 6.000s 2009.975us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 38.000s 4114.278us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 601.632us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 69.477us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 32.960us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 23.833us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 7.000s 106.864us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 7.000s 106.864us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.430us 1 1 100.00
spi_host_csr_rw 1.000s 19.910us 1 1 100.00
spi_host_csr_aliasing 1.000s 24.102us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 20.685us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.430us 1 1 100.00
spi_host_csr_rw 1.000s 19.910us 1 1 100.00
spi_host_csr_aliasing 1.000s 24.102us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 20.685us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 7.000s 72.596us 1 1 100.00
spi_host_sec_cm 2.000s 72.192us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 7.000s 72.596us 1 1 100.00