Simulation Results: sram_ctrl/main

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.86 %
  • code
  • 95.69 %
  • assert
  • 98.10 %
  • func
  • 93.80 %
  • block
  • 96.03 %
  • line
  • 96.75 %
  • branch
  • 94.17 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 9777.939us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 21.969us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 27.090us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 101.397us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.775us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 3159.993us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 27.090us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.775us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 125.000s 13164.049us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 48.000s 5707.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 14.000s 7183.769us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 192.000s 23659.200us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 133.000s 60990.701us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 56.000s 15605.251us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 24.000s 17985.031us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 1041.855us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 2768.592us 1 1 100.00
sram_ctrl_partial_access_b2b 199.000s 16186.324us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 1781.982us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 664.834us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 1302.143us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 490.752us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1345.492us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 270.000s 72281.849us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 6.000s 53.624us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 92.074us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 92.074us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 21.969us 1 1 100.00
sram_ctrl_csr_rw 1.000s 27.090us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.775us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 83.944us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 21.969us 1 1 100.00
sram_ctrl_csr_rw 1.000s 27.090us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 35.775us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 83.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 7646.105us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 1042.888us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 166.303us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 1042.888us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 166.303us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 490.752us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 490.752us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 27.090us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1041.855us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1041.855us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1041.855us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 24.000s 17985.031us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 971.025us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 7646.105us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 712.199us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 9777.939us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 9777.939us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 1041.855us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 1042.888us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 24.000s 17985.031us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 1042.888us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1042.888us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 9777.939us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1042.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 16.000s 1639.502us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 54785354203021391753329947932909026357942806931306844065631941386797815861023 86
UVM_INFO @ 1781982174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 2893269842653138751834979172723621538154659481590934666227691334289096819449 86
UVM_INFO @ 664834419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 107649232512810313834477918662664891919119558964755124737289463080394951463614 86
UVM_INFO @ 1302142762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---