Simulation Results: uart

 
14/07/2026 19:40:28 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.82 %
  • code
  • 96.65 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 88.74 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 9.000s 5560.795us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 18.050us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 7.000s 13.416us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 158.758us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 45.171us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 3.000s 25.498us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 7.000s 13.416us 1 1 100.00
uart_csr_aliasing 1.000s 45.171us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 9.000s 15041.891us 1 1 100.00
parity 2 2 100.00
uart_smoke 9.000s 5560.795us 1 1 100.00
uart_tx_rx 9.000s 15041.891us 1 1 100.00
parity_error 2 2 100.00
uart_intr 16.000s 56219.688us 1 1 100.00
uart_rx_parity_err 103.000s 169666.340us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 9.000s 15041.891us 1 1 100.00
uart_intr 16.000s 56219.688us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 62.000s 198947.749us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 45.000s 68698.537us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 25.000s 23109.622us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 16.000s 56219.688us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 16.000s 56219.688us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 16.000s 56219.688us 1 1 100.00
perf 1 1 100.00
uart_perf 20.000s 4876.494us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.000s 3006.920us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.000s 3006.920us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.000s 1489.696us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.000s 4978.021us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 5.000s 1445.256us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 26.000s 6535.591us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 166.000s 93480.470us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 52.000s 133244.520us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 15.204us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 55.438us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 298.226us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 298.226us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 18.050us 1 1 100.00
uart_csr_rw 7.000s 13.416us 1 1 100.00
uart_csr_aliasing 1.000s 45.171us 1 1 100.00
uart_same_csr_outstanding 1.000s 60.937us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 18.050us 1 1 100.00
uart_csr_rw 7.000s 13.416us 1 1 100.00
uart_csr_aliasing 1.000s 45.171us 1 1 100.00
uart_same_csr_outstanding 1.000s 60.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 98.385us 1 1 100.00
uart_tl_intg_err 1.000s 60.688us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 60.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 30.000s 16877.436us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 21085283930325354455602472214588779834647464021545358346672751549246469416884 83
UVM_ERROR @ 203296078 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 203296078 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 203296078 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 203296078 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark