Simulation Results: ac_range_check

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.77 %
  • code
  • 93.00 %
  • assert
  • 97.75 %
  • func
  • 57.56 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 19.000s 953.500us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 43.000s 5105.633us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 61.913us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 72.212us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 21.000s 1288.133us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1707.446us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 12.000s 26.595us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 72.212us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1707.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 28.640us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 20.000s 2153.813us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 83.000s 1941.083us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 34.238us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 45.207us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 79.440us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 79.440us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 61.913us 1 1 100.00
ac_range_check_csr_rw 2.000s 72.212us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1707.446us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 752.124us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 61.913us 1 1 100.00
ac_range_check_csr_rw 2.000s 72.212us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1707.446us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 752.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 8625.380us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 8625.380us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 8625.380us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 8625.380us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 75.000s 9413.973us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 13.178us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 376.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 276.000s 1642.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 33.000s 1644.292us 1 1 100.00