Simulation Results: aes/gcm_masked

 
15/07/2026 19:40:28 DVSim: v1.49.12 sha: 62fb2eb json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.94 %
  • code
  • 95.72 %
  • assert
  • 98.29 %
  • func
  • 66.82 %
  • block
  • 95.91 %
  • line
  • 97.55 %
  • branch
  • 89.88 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 69.246us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 87.871us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 7.000s 103.698us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 55.402us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 9.000s 444.874us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 7.000s 93.775us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 59.943us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 55.402us 1 1 100.00
aes_csr_aliasing 7.000s 93.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 87.871us 1 1 100.00
aes_config_error 7.000s 78.907us 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 87.871us 1 1 100.00
aes_config_error 7.000s 78.907us 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 250.321us 1 1 100.00
aes_b2b 10.000s 253.817us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 87.871us 1 1 100.00
aes_config_error 7.000s 78.907us 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
aes_alert_reset 2.000s 125.161us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 97.517us 1 1 100.00
aes_config_error 7.000s 78.907us 1 1 100.00
aes_alert_reset 2.000s 125.161us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 418.164us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 630.567us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 703.878us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 125.161us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 250.321us 1 1 100.00
aes_sideload 3.000s 96.099us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 158.793us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 7.000s 258.802us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 121.158us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 281.357us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 130.720us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 130.720us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 7.000s 103.698us 1 1 100.00
aes_csr_rw 2.000s 55.402us 1 1 100.00
aes_csr_aliasing 7.000s 93.775us 1 1 100.00
aes_same_csr_outstanding 2.000s 287.028us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 7.000s 103.698us 1 1 100.00
aes_csr_rw 2.000s 55.402us 1 1 100.00
aes_csr_aliasing 7.000s 93.775us 1 1 100.00
aes_same_csr_outstanding 2.000s 287.028us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 115.268us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 1470.000s 200000.000us 0 1 0.00
aes_control_fi 3.000s 76.628us 1 1 100.00
aes_cipher_fi 2.000s 76.452us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 148.783us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 148.783us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 148.783us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 148.783us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 915.341us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 2189.182us 1 1 100.00
aes_tl_intg_err 1.000s 146.013us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 146.013us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 125.161us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 148.783us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 148.783us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 87.871us 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
aes_alert_reset 2.000s 125.161us 1 1 100.00
aes_core_fi 7.000s 116.529us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 121.158us 1 1 100.00
aes_config_error 7.000s 78.907us 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
aes_core_fi 7.000s 116.529us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 148.783us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 7.000s 175.732us 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 250.321us 1 1 100.00
aes_sideload 3.000s 96.099us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 7.000s 175.732us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 7.000s 175.732us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 7.000s 175.732us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 7.000s 175.732us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 7.000s 175.732us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 250.321us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 1470.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 1470.000s 200000.000us 0 1 0.00
aes_control_fi 3.000s 76.628us 1 1 100.00
aes_cipher_fi 2.000s 76.452us 1 1 100.00
aes_ctr_fi 2.000s 129.873us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 1470.000s 200000.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 1470.000s 200000.000us 0 1 0.00
aes_control_fi 3.000s 76.628us 1 1 100.00
aes_cipher_fi 2.000s 76.452us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 76.452us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 1470.000s 200000.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 1470.000s 200000.000us 0 1 0.00
aes_control_fi 3.000s 76.628us 1 1 100.00
aes_ctr_fi 2.000s 129.873us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 1470.000s 200000.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 1470.000s 200000.000us 0 1 0.00
aes_control_fi 3.000s 76.628us 1 1 100.00
aes_cipher_fi 2.000s 76.452us 1 1 100.00
aes_ctr_fi 2.000s 129.873us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 125.161us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 1470.000s 200000.000us 0 1 0.00
aes_control_fi 3.000s 76.628us 1 1 100.00
aes_cipher_fi 2.000s 76.452us 1 1 100.00
aes_ctr_fi 2.000s 129.873us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 1470.000s 200000.000us 0 1 0.00
aes_control_fi 3.000s 76.628us 1 1 100.00
aes_cipher_fi 2.000s 76.452us 1 1 100.00
aes_ctr_fi 2.000s 129.873us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 1470.000s 200000.000us 0 1 0.00
aes_control_fi 3.000s 76.628us 1 1 100.00
aes_ctr_fi 2.000s 129.873us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 111.263us 1 1 100.00
aes_fi 1470.000s 200000.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 1470.000s 200000.000us 0 1 0.00
aes_control_fi 3.000s 76.628us 1 1 100.00
aes_cipher_fi 2.000s 76.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 7.000s 421.334us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_fi 93426409375999716821821996586319153471272382492011150885212471565495677394450 15998432
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:1082) virtual_sequencer [aes_stress_vseq] 1 test run
aes_stress_all_with_rand_reset 36298969684358409450894565360699197749606611685647523707389766138459636373210 327
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0